HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 1 1 ; ************************************************** ************************* 2 ; * 3 ; HC908 Debug Monitor V1.0 * 4 ; George Heron, N2APB * 5 ; 12/2002 * 6 ; * 7 ; This program is a simple, low-level debug monitor developed to support * 8 ; the projects based on the "HC908 Daughtercard" project described * 9 ; in QRP Homebrewer magazine (published by the NJQRP Club), in QRP * 10 ; Quarterly magazine (published by QRP ARCI), and on the website of the * 11 ; New Jersey QRP Club (www.njqrp.org) * 12 ; * 13 ; The operator interfaces to the HC908 Debug Monitor by means of a dumb * 14 ; terminal connected to the RS-232 serial port of the MPU daughtercard. * 15 ; Through the Monitor's command/response structure, the operator may edit * 16 ; memory amd MPU registers, set and reset breakpoint s, "go" or single step * 17 ; from any executable location in the loaded program, load S record files * 18 ; sent by the terminal, program Flash memory from the downloaded S records, * 19 ; and read input ports and set output ports. * 20 ; * 21 ; The HC908 Debug Monitor is programmed into all HC908 Daughtercards after * 22 ; manufacture. In some instances, another software program may also be * 23 ; programmed in the HC908 Daughtercard at time of manufacture, providing * 24 ; the customer with one of a growing number of software applications for * 25 ; this product (e.g., the Digital Breadboard, the Antenna Analyzer, HC908 * 26 ; Commander, the HC908 Digital VFO and others). * 27 ; * 28 ; As mentioned, the HC908 Daughtercard and its debug monitor provides the * 29 ; user with an ability to program the permament and nonvolatile "flash" * HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 2 30 ; memory directly from downloaded "S records". An S record file is a common * 31 ; format for the assembled or compiled 68HC908 MPU binary code, as * 32 ; used in most Motorola-based processors and tools. Thus, when a user * 33 ; wishes to load a program other than what arrived on his HC908 * 34 ; Daughtercard, he may download any of the available S record files from the* 35 ; project's Internet website and "burn" the program into the MPU's flash * 36 ; memory, thus making the program permanent and available for his use. In * 37 ; this way, the user is able to change the HC908 Daughtercard's * 38 ; "personality" without any other tools than a terminal program connected * 39 ; to the Daughtercard on its serial port. * 40 ; * 41 ; Most "dumb terminals" may be used to communicate with the HC908 Debug * 42 ; Monitor. Examples of such programs include HyperTerminal, Red Ryder, * 43 ; ProComm and PCPlus. However, a useful, public domain (freeware) terminal * 44 ; program called "Tera Term" is also available to run on Microsoft Windows * 45 ; platforms. Tera Term has a convenient scripting ability that can be * 46 ; invoked to send an S record file (like a new software program) to your * 47 ; HC908 Daughtercard for flash programming by the Monitor. The Tera Term * 48 ; terminal program and its S record transfer script are provided on the * 49 ; HC908 project website for users to download and use on their systems. * 50 ; * 51 ; There are many more features and details concernin g the use of the HC908 * 52 ; Debug Monitor on the HC908 Daughtercard-based projects. Please refer to * 53 ; written documentation provided with the Monitor and Daughtercard for the * 54 ; latest and authoritative information concerning capabilities and use. * 55 ; * 56 ; Questions may be addressed to me by email and I'll do my best to help out.* 57 ; 58 ; v1 Dec 2002 Initial release 59 ; v2a May 5, 2003 Removed $803C hook into User Space to reduce HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 3 60 ; complexity and chance for user to mess up by 61 ; inadvertently overwriting the hook code 62 ; v2b June 8, 2003 Corrected comment for PIT interrupt vector code (FFF6+FFF7) 63 ; * 64 ; George Heron, N2APB * 65 ; email: n2apb@amsat.org * 66 ; * 67 ; ************************************************** ************************* 68 ; GNU Public License * 69 ; * 70 ; This program is free software; you can redistrib ute it and/or modify * 71 ; it under the terms of the GNU General Public License as published by * 72 ; the Free Software Foundation; either version 2 of the License, or * 73 ; (at your option) any later version. * 74 ; * 75 ; This program is distributed in the hope that it will be useful, * 76 ; but WITHOUT ANY WARRANTY; without even the implied warranty of * 77 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 78 ; GNU General Public License for more details. * 79 ; * 80 ; You should have received a copy of the GNU General Public License * 81 ; along with this program; if not, write to the Free Software * 82 ; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * 83 ; * 84 ; See license.txt file for details * 85 ; * 86 ;*************************************************** ************************* 87 ; Credits: * 88 ; * HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 4 89 ; Major portions of this program were adapted from the Pony 68HC908 Debug * 90 ; Monitor V1.4 by Larry Bateman. Copyright (c) 2000, L3 Systems. * 91 ; * 92 ; Portions borrowed from Motorola's "MC68HC908GP32 User Bootloader", * 93 ; Copyright (c) Motorola 2000. Written by DGJ Klotz Rev ES 1.0 26-Feb-00 * 94 ; * 95 ; ************************************************** ************************* 96 0000 97 $BASE 10T 98 0000 99 include "../ab_regs.asm" ; MC68HC908GP32 register defimitions 100 ; 68HC908AB32 Equates 101 0000 102 PTA EQU $0000 ; Ports and data direction 0000 103 PORTA EQU $0000 0000 104 PTB EQU $0001 0000 105 PORTB EQU $0001 0000 106 PTC EQU $0002 0000 107 PORTC EQU $0002 0000 108 PTD EQU $0003 0000 109 PORTD EQU $0003 0000 110 DDRA EQU $0004 0000 111 DDRB EQU $0005 0000 112 DDRC EQU $0006 0000 113 DDRD EQU $0007 114 0000 115 PTE EQU $0008 0000 116 PORTE EQU $0008 0000 117 PTF EQU $0009 0000 118 PORTF EQU $0009 0000 119 PTG EQU $000A 0000 120 PORTG EQU $000A 0000 121 PTH EQU $000B 0000 122 PORTH EQU $000B 123 0000 124 DDRE EQU $000C 0000 125 DDRF EQU $000D 0000 126 DDRG EQU $000E 0000 127 DDRH EQU $000F 128 129 ;* Serial Peripheral Interface Module (SPI) ******************************** 130 0000 131 spcr equ $10 ; SPI Control Register 0000 132 SPRIE equ 7 ; SPI receiver interrupt enable bit 0000 133 SPMSTR equ 5 ; SPI master bit 0000 134 CPOL equ 4 ; clock HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 5 polarity bit 0000 135 CPHA equ 3 ; clock phase bit 0000 136 SPWOM equ 2 ; SPI wired-or mode bit 0000 137 SPE equ 1 ; SPI enable 0000 138 SPTIE equ 0 ; SPI transmit interrupt enable 139 0000 140 spscr equ $11 ; SPI Status and Control Register 0000 141 SPRF equ 7 ; SPI receiver full bit 0000 142 ERRIE equ 6 ; error interrupt enable bit 0000 143 OVRF equ 5 ; overflow bit 0000 144 MODF equ 4 ; mode fault bit 0000 145 SPTE equ 3 ; SPI transmitter empty bit 0000 146 MODFEN equ 2 ; mode fault enable bit 0000 147 SPR1 equ 1 ; SPI baud rate 0000 148 SPR0 equ 0 ; select bits 149 0000 150 spdr equ $12 ; SPI Data Register 151 152 153 ;* Serial Communications Interface (SCI) ********* ************************* 154 0000 155 scc1 equ $13 ; SCI Control Register 1 0000 156 LOOPS equ 7 ; loop mode select bit 0000 157 ENSCI equ 6 ; enable SCI bit 0000 158 TXINV equ 5 ; transmit inversion bit 0000 159 M equ 4 ; mode bit 0000 160 WAKE equ 3 ; wakeup condition bit 0000 161 ILTY equ 2 ; idle line type bit 0000 162 PEN equ 1 ; parity enable bit 0000 163 PTY equ 0 ; parity bit 164 0000 165 scc2 equ $14 ; SCI Control Register 2 0000 166 SCTIE equ 7 ; SCI transmit interrupt enable bit 0000 167 TCIE equ 6 ; transmissi on complete int enable bit HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 6 0000 168 SCRIE equ 5 ; SCI receive interrupt enable bit 0000 169 ILIE equ 4 ; idle line interrupt enable bit 0000 170 TE equ 3 ; transmitte r enable bit 0000 171 RE equ 2 ; receiver enable bit 0000 172 RWU equ 1 ; receiver wakeup bit 0000 173 SBK equ 0 ; send break bit 174 0000 175 scc3 equ $15 ; SCI Control Register 3 0000 176 R8 equ 7 ; received bit 8 0000 177 T8 equ 6 ; transmitte d bit 8 0000 178 ORIE equ 3 ; receiver overrun interrupt enable bit 0000 179 NEIE equ 2 ; receiver noise error int enable bit 0000 180 FEIE equ 1 ; receiver framing error int enable bit 0000 181 PEIE equ 0 ; receiver parity error int enable bit 182 0000 183 scs1 equ $16 ; SCI Status Register 1 0000 184 SCTE equ 7 ; SCI transmitter empty bit 0000 185 TC equ 6 ; transmissi on complete bit 0000 186 SCRF equ 5 ; SCI receiver full bit 0000 187 IDLE equ 4 ; receiver idle bit 0000 188 OR equ 3 ; receiver overrun bit 0000 189 NF equ 2 ; receiver noise flag bit 0000 190 FE equ 1 ; receiver framing error bit 0000 191 PE equ 0 ; receiver parity error bit 192 0000 193 scs2 equ $17 ; SCI Status Register 2 0000 194 BKF equ 1 ; break flag bit 0000 195 RPF equ 0 ; reception in progress flag bit 196 ; 0000 197 scdr equ $18 ; SCI Data Register 0000 198 scbr equ $19 ; SCI Baud Rate Register HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 7 199 200 201 ;* External Interrupt (IRQ) ********************** ************************* 202 0000 203 intscr equ $1D ; IRQ Status and Control Register 0000 204 IRQF equ 3 ; IRQ flag bit 0000 205 ACK equ 2 ; IRQ interrupt request acknowledge bit 0000 206 IMASK equ 1 ; IRQ interrupt mask bit 0000 207 MODE equ 0 ; IRQ edge/level select bit 208 0000 209 ISCR EQU $001A 210 211 212 ;* Keyboard Interrupt Module (KBI) *************** ************************* 213 0000 214 intkbscr equ $1B ; Keyboard Status and Control Register 0000 215 KBSCR EQU $001B 0000 216 KEYF equ 3 ; keyboard flag bit 0000 217 ACKK equ 2 ; keyboard acknowledge bit 0000 218 IMASKK equ 1 ; keyboard interrupt mask bit 0000 219 MODEK equ 0 ; keyboard triggering sensitivity bit 220 ; 0000 221 intkbier equ $21 ; Keyboard Interrupt Enable Register 0000 222 KBICR EQU $0021 0000 223 KBIE4 equ 4 0000 224 KBIE3 equ 3 0000 225 KBIE2 equ 2 0000 226 KBIE1 equ 1 0000 227 KBIE0 equ 0 228 229 230 ;* Clock Generator Module (CGMC) ***************** ************************* 231 0000 232 pctl equ $1C ; PLL Control Register 0000 233 PLLIE equ 7 ; PLL interrupt enable bit 0000 234 PLLF equ 6 ; PLL interrupt flag bit 0000 235 PLLON equ 5 ; PLL on bit 0000 236 BCS equ 4 ; base clock select bit 237 ; 0000 238 pbwc equ $1D ; PLL Bandwidth HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 8 Control Register 0000 239 AUTO equ 7 ; automatic bandwidth control bit 0000 240 LOCK equ 6 ; lock indicator bit 0000 241 ACQ equ 5 ; acquisitio n mode bit 242 0000 243 PPG equ $001E ; PLL Programmin g Register 244 ; Multiplier Select bits [7:4] 245 ; VCO Frequency Multiplier bit [3:0] 246 247 ;* Configuration Registers (CONFIG) ************** ************************* 248 0000 249 CONFIG EQU $001F ; System configuration 0000 250 CONFIG1 EQU $001F 0000 251 CONFIG2 EQU $003F 252 0000 253 TASC EQU $0020 ; Timer A 0000 254 TACNTH EQU $0022 0000 255 TACNTL EQU $0023 0000 256 TAMODH EQU $0024 0000 257 TAMODL EQU $0025 0000 258 TASC0 EQU $0026 0000 259 TACH0H EQU $0027 0000 260 TACH0L EQU $0028 0000 261 TASC1 EQU $0029 0000 262 TACH1H EQU $002A 0000 263 TACH1L EQU $002B 0000 264 TASC2 EQU $002C 0000 265 TACH2H EQU $002D 0000 266 TACH2L EQU $002E 0000 267 TASC3 EQU $002F 0000 268 TACH3H EQU $0030 0000 269 TACH3L EQU $0031 270 0000 271 TBSC EQU $0041 ; Timer B 0000 272 TBCNTH EQU $0042 0000 273 TBCNTL EQU $0043 0000 274 TBMODH EQU $0044 0000 275 TBMODL EQU $0045 0000 276 TBSC0 EQU $0046 0000 277 TBCH0H EQU $0047 0000 278 TBCH0L EQU $0048 0000 279 TBSC1 EQU $0049 0000 280 TBCH1H EQU $004A 0000 281 TBCH1L EQU $004B 0000 282 TBSC2 EQU $0032 0000 283 TBCH2H EQU $0033 0000 284 TBCH2L EQU $0034 0000 285 TBSC3 EQU $0035 0000 286 TBCH3H EQU $0036 0000 287 TBCH3L EQU $0037 288 HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 9 0000 289 TSC EQU $004B ; Timer 0000 290 TCNTH EQU $004C 0000 291 TCNTL EQU $004D 0000 292 TMODH EQU $004E 0000 293 TMODL EQU $004F 294 295 296 297 ;* Analog-to-Digital Converter (ADC) ************* ************************* 298 0000 299 adscr equ $38 ; ADC Status and Control Register 0000 300 COCO equ 7 ; conversion s complete flag 0000 301 AIEN equ 6 ; ADC interrupt enable bit 0000 302 ADCO equ 5 ; ADC continuous conversion bit 0000 303 ADCH4 equ 4 ; \ 0000 304 ADCH3 equ 3 ; \ 0000 305 ADCH2 equ 2 ; ADC channel select bits 0000 306 ADCH1 equ 1 ; / 0000 307 ADCH0 equ 0 ; / 308 0000 309 adr equ $39 ; ADC Data Register 310 0000 311 adclk equ $3A ; ADC Clock Register 0000 312 ADIV2 equ 7 ; \ 0000 313 ADIV1 equ 6 ; ADC clock prescaler bits 0000 314 ADIV0 equ 5 ; / 0000 315 ADICLK equ 4 ; ADC input clock select bit 316 317 ;* Pullup Registers ******************************* ******* 318 0000 319 PTDPUE EQU $003D 0000 320 PTFPUE EQU $003E 0000 321 PRTFPU EQU $003E 322 323 ;* System Integration Module (SIM) *************** ************************* 324 0000 325 sbsr equ $FE00 ; SIM Break Status Register 0000 326 SBSW equ 1 ; SIM break stop/wait 327 0000 328 srsr equ $FE01 ; SIM Reset Status Register 0000 329 POR equ 7 ; power-on reset bit 0000 330 PIN equ 6 ; external HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 10 reset bit 0000 331 COP equ 5 ; COP reset bit 0000 332 ILOP equ 4 ; illegal opcode reset bit 0000 333 ILAD equ 3 ; illegal opcode address reset bit 334 ;MODRST equ 2 ; monitor mode entry module reset bit 0000 335 LVI equ 1 ; LVI reset bit 336 0000 337 sbfcr equ $FE03 ; SIM Break Flag Control Register 0000 338 BCFE equ 7 ; break clear flag enable bit 339 340 ;* Flash Memory ********************************** ************************* 341 0000 342 flcr equ $FE08 ; Flash Control Register 0000 343 HVEN equ %00001000 ; high-voltage enable bit mask 0000 344 MASS equ %00000100 ; mass erase control bit mask 0000 345 ERASE equ %00000010 ; erase control bit mask 0000 346 PGM equ %00000001 ; program control bit mask 347 0000 348 flbpr equ $FF7E ; Flash Block Protect Register 349 350 ;* Breakpoint Module (BRK) *********************** ************************* 351 0000 352 brkh equ $FE0C ; Break Address Register High 0000 353 brkl equ $FE0D ; Break Address Register Low 0000 354 brkscr equ $FE0E ; Break Status and Control Register 0000 355 BRKE equ 7 ; break enable bit 0000 356 BRKA equ 6 ; break active bit 357 358 ;* Low-Voltage Inhibit (LVI) ********************* ************************* 359 0000 360 lvisr equ $FE0F ; LVI Status Register 0000 361 LVIOUT equ 7 ; LVI output bit 362 363 ;* EEPROM programming registers ******************* *************************** HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 11 364 0000 365 EEDIVHNVR equ $FE10 366 0000 367 EEDIVLNVR equ $FE11 368 0000 369 EEDIVH equ $FE1A 370 0000 371 EEDIVL equ $FE1B 372 0000 373 eenvr equ $FE1C ;EEPROM Array Config Reg 0000 374 EEPRTCT equ 16 ;protection bit 0000 375 EEBP3 equ 8 ;block potection bit 3 0000 376 EEBP2 equ 4 ;block potection bit 2 0000 377 EEBP1 equ 2 ;block potection bit 1 0000 378 EEBP0 equ 1 ;block potection bit 0 379 0000 380 eecr equ $FE1D ;EEPROM Control Reg 0000 381 EEDUM equ 128 ;dummy bit 0000 382 EEOFF equ 32 ;power off 0000 383 EERAS1 equ 16 ;erase/program mode select bit 1 0000 384 EERAS0 equ 8 ;erase/program mode select bit 0 0000 385 EELAT equ 4 ;latch control 0000 386 EEAUTO equ 2 ;automatic termination of prgm/erase cycle 0000 387 EEPGM equ 1 ;program/erase enable 388 0000 389 EEACR equ $FE1F 390 391 ;* Computer Operating Properly (COP) ************* ************************* 392 0000 393 copctl equ $FFFF ; COP Control Register 394 395 ;*************************************************** ********* 396 ; VECTORS 397 ;*************************************************** ********* 398 0000 399 dbg_vectors equ $FAD0 ; Debug Vectors 400 0000 401 Vectors: equ $ffd0 402 0000 403 ivadc: equ $ffd0 ; Vector for A/D HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 12 conversion Complete 0000 404 ivkey: equ $ffd2 ; Vector for Keyboard 0000 405 ivsctx: equ $ffd4 ; Vector for SCI Tx 0000 406 ivscrx: equ $ffd6 ; Vector for SCI Rx 0000 407 ivscer: equ $ffd8 ; Vector for SCI Error 0000 408 equ $ffda ; Reserved 0000 409 equ $ffdc ; Reserved 0000 410 ivtb3: equ $ffde ; TIMB Channel 3 Vector 0000 411 ivtb2: equ $ffe0 ; TIMB Channel 2 Vector 0000 412 ivsptx: equ $ffe2 ; Vector for SPI Tx 0000 413 ivsprx: equ $ffe4 ; Vector for SPI Rx 0000 414 ivtbof: equ $ffe6 ; TIMB Overflow Vector 0000 415 ivtb1: equ $ffe8 ; TIMB Channel 1 Vector 0000 416 ivtb0: equ $ffea ; TIMB Channel 0 Vector 0000 417 ivtao: equ $ffec ; TIMA Overflow Vector 0000 418 ivt1c1: equ $ffee ; TIMA Channel 3 Vector 0000 419 ivta2: equ $fff0 ; TIMA Channel 2 Vector 0000 420 ivta1: equ $fff2 ; TIMA Channel 1 Vector 0000 421 ivta0: equ $fff4 ; TIMA Channel 0 Vector 0000 422 ivtof: equ $fff6 ; TIM Overflow Vector 0000 423 ivpll: equ $fff8 ; PLL Vector 0000 424 ivirq: equ $fffa ; ~IRQ1 Vector 0000 425 ivswi: equ $fffc ; SWI Vector 0000 426 ivrst: equ $fffe ; Reset Vector 427 428 429 ;*************************************************** ********* 430 ;* Memory Map 431 ;*************************************************** ********* 432 0000 433 ram_start equ $0050 ; start of RAM 0000 434 zpage_end equ $00FF ; End of zero page ram 0000 435 extraram equ $0100 ; Start of Extra RAM 0000 436 usr_stack equ $01ff ; Bottom of user stack 0000 437 ram_last equ $023F ; last RAM location 0000 438 rom_start equ $8000 ; start of ROM 0000 439 rom_last equ $FAFF ; last ROM location ($FDFF??) 440 HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 13 441 442 ;(C)opywrite P&E Microcomputer Systems, 2000 (www.pemicro.com) 443 ; You may use this code freely as long as this copyright notice 444 ; and website address is included and un-modified. 445 0000 446 include "../macros.asm" ; Macro instruction definition 447 ; -------------------------------------------------- ----------------- 448 ; Macro Definitions 449 ; -------------------------------------------------- ----------------- 450 0000 451 #macro aax macro 452 psha 453 pshx 454 add 1,sp 455 pulx 456 tax 457 bcc *+7 ; Branch to below 458 pshh 459 inc 1,sp 460 pulh 461 ; Branch to here 462 pula 0000 463 #macroend 464 0000 465 #macro inch macro 466 pshh 467 inc 1,sp 468 pulh 0000 469 #macroend 470 0000 471 #macro tha macro 472 pshh 473 pula 0000 474 #macroend 475 0000 476 #macro tah macro 477 psha 478 pulh 0000 479 #macroend 480 0000 481 #macro pshhx macro 482 pshx 483 pshh 0000 484 #macroend 485 0000 486 #macro pulhx macro 487 pulh 488 pulx 0000 489 #macroend 490 0000 491 #macro ldhxx macro 492 lda ,x 493 ldx 1,x HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 14 494 psha 495 pulh 0000 496 #macroend 497 0000 498 include "../local.asm" ; Local variables 499 ; 500 ; Conditional Assembly Directives *************** ************************* 501 ; 502 0000 503 #setnot HYPERTERM ; enable slow Hyperterminal communications 504 505 ; 506 ; Microcontroller Peripheral Equates ************ ************************* 507 ; 508 0000 509 boot_start equ $E000 ; start of protected Bootloader 0000 510 flash_protect equ {(boot_start>7)&$FF} ; Flash Block Protect Reg value 0000 511 flash_page equ 128T ; Flash Erase Page size 512 0000 513 init_config1 equ %00000011 ; initial Configurat ion Register 1 514 ; Bit_7=0 - LVISTOP - LVI disabled during stop mode 515 ; Bit_6 unused 516 ; Bit_5=0 - LVIRSTD - LVI reset enabled during run mode 517 ; Bit_4=0 - LVIPWRD - Power enabled to LVI module 518 ; Bit_3=0 - SSREC - Stop recovery after 4096 cycles 519 ; Bit_2=0 - COPRS - COP rate (2**18 - 2**4) 520 ; Bit_1=1 - STOP - Stop Instruction disabled 521 ; Bit_0=1 - COPD - COP Disabled 522 ; 0000 523 RXBLEN equ 14T ; Serial I/O Receive buffer length 0000 524 STACK_ALLOC equ 32T ; Monitor Stack Allocation 525 ; 0000 526 init_scc1 equ %01000000 ; enable SCI, 8-bits, no par, 1 stop 0000 527 init_scc2 equ %00001100 ; no interupts, rcvr and tmtr enabled 0000 528 init_scbr equ %00000011 ; set SCI for 9600 baud 529 ; 530 ; ASCII character definitions 531 0000 532 SPACE equ $20 ; ASCII space HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 15 0000 533 CR equ $0D ; ASCII carriage return 0000 534 LF equ $0A ; ASCII linefeed 0000 535 NUL equ $00 ; ASCII linefeed 0000 536 BS equ $08 ; ASCII Backspace key 0000 537 XOFF equ $13 ; ASCII X-Off key (^S or DC3) 0000 538 XON equ $11 ; ASCII X-On key (^S or DC1) 0000 539 ESC equ $1B ; ASCII Escape Character 540 541 ;--------------------------------------------------- ---- 542 ; TIMING FOR fbus = 0.407 us 543 ;the internal clock fBUS runs at 1/2.4576 ^6 = 0.407 uS. 544 ;The DBNZ instruction takes 3 cycles, which makes 1.22 uS 545 ;us5 EQU 5 ;5 * 1.22 = 6.1 uS 546 ;us10 EQU 9 ;9 * 1.22 = 10.9 uS 547 ;us30 EQU 25 ;25 * 1.22 = 30.5 uS 548 ;us100 EQU 82 ;82 * 1.22 = 100 549 ;ms1 EQU 10 ;10 * 82 * 1.22 = 1.00 mS 550 551 ;--------------------------------------------------- ----- 552 ; TIMING FOR fbus = 0.115 us 553 ;The DBNZ instruction takes 3 cycles, which makes 0.344 uS 0000 554 us1 EQU 3 ;3 * 0.344 = 1.032 uS 0000 555 us5 EQU 18 ;18 * 0.344 = 6.1 uS 0000 556 us10 EQU 32 ;32 * 0.344 = 10.9 uS 0000 557 us30 EQU 89 ;89 * 0.344 = 30.5 uS 0000 558 us50 EQU 148 ;148 * 0.344 = 51 us 0000 559 ms1 EQU 36 ;36 * 82 * 0.344 = 1.00 mS 560 0000 561 tpgs EQU us5 ;times taken from MC68HC908AB32/D rev 1 0000 562 tnvs EQU us10 0000 563 tprog EQU us30 0000 564 tnvh EQU us5 0000 565 terase EQU ms1 566 567 ; User Base RAM 568 0050 569 org $50 0050 570 _count rmb 1 ; Byte Counter for s record download 0051 571 _temp_sp rmb 2 ; Temporary stack pointer 572 573 ; User stack - Hex 3ff HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 16 574 03FF 575 org $3FF 03FF 576 _user_stack rmb 1 ; Position to Initialize user stack 577 578 ; Monitor RAM - Hex 400-44F 579 0400 580 org $400 0400 581 _hbufpos rmb 2 ; buffer position temp storage 0402 582 _tempx rmb 2 ; Temporary h:x register storage 0404 583 _stack_save rmb 2 ; Stack save 0406 584 _last_break rmb 2 ; Save last break, to reset break 585 ; when resuming 0408 586 _h_save rmb 1 ; h-reg save 0409 587 _state rmb 1 ; State after break point 040A 588 _inbuf rmb RXBLEN ; Input Buffer 589 590 ; Monitor stack, initialize at end of RAM Hex 23F 591 044F 592 org $44F 044F 593 _mon_stack rmb 1 ; Position of monitor stack 594 EF00 595 org $EF00 EF00 8040 596 _user_reset fdb $8040 ; pointer to start User Application 597 598 ;*************************************************** ********* 599 ; Power-on Reset 600 ;*************************************************** ********* 601 __start: 602 _bootreset: 603 ; Launch the bootloader from power-on reset. 604 EF02 [02] 9B 605 sei ; disable all interupts EF03 [03] 450450 606 ldhx #_mon_stack+1 ; initialize EF06 [02] 94 607 txs ; the stack pointer 608 EF07 [05] CDF200 609 jsr PLLset ; change bus speed 610 611 ; Initialize the SCI. 612 EF0A [04] 6E0319 613 mov #init_scbr,scbr ; initialize baud rate EF0D [04] 6E4013 614 mov #init_scc1,scc1 ; initialize HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 17 SCI Control Register 1 EF10 [04] 6E0C14 615 mov #init_scc2,scc2 ; initialize SCI Control Register 2 EF13 [04] 6E031F 616 mov #init_config1,config1 ; init Configuration Register 1 617 618 ; Test Port F7 for "Monitor Jumper" 619 ; Entry to Monitor = jumper OFF ==> F7 = 1 620 ; Entry to User Pgm = jumper ON ==> F7 = 0 621 EF16 [04] 6E400D 622 mov #$40,ddrf ;set portf bits 7,5,4,3,2,1,0 as inputs, bit 6 (LED) as output EF19 [04] 6EB83E 623 mov #$B8,prtfpu ;assign pullups to Port F bits 7,5,4,3 EF1C [04] 1D09 624 bclr 6,portf ;turn LED on continuously while in monitor EF1E [05] 0F0909 625 brclr 7,portf,MonStart ;go start Monitor if "Monitor Jumper" is in place EF21 [03] 4503FF 626 ldhx #_user_stack ;else init user SP EF24 [05] CDF149 627 jsr _save_sp ; in _user_stack area EF27 [05] CD8040 628 jsr $8040 ; and go start User application at $8040 629 630 MonStart: EF2A [03] 450050 631 ldhx #ram_start EF2D [02] 7F 632 clrRAM: clr ,x ;Clear RAM EF2E [02] AF01 633 aix #1 EF30 [03] 650240 634 cphx #ram_last+1 EF33 [03] 26F8 635 bne clrRAM 636 EF35 [05] CDEF6E 637 jsr _init_ustack ;Initialize user stack 638 EF38 [01] 9D 639 nop EF39 [01] 9D 640 nop EF3A [01] 9D 641 nop 642 643 ; Boot start 644 _boot: EF3B [04] C7FFFF 645 sta copctl ;clear the COP counter EF3E [02] A6FF 646 lda #$FF EF40 [05] CDF299 647 jsr _delay ;delay just a bit EF43 [03] 45F3A3 648 ldhx #_PWR_MSG ;point to monitor sign-on message EF46 [05] CDF60A 649 jsr _puts ;and display it 650 _main: EF49 [03] 45F308 651 ldhx #_PROMPT ; Print prompt EF4C [05] CDF60A 652 jsr _puts EF4F [05] CDF4EE 653 jsr _gets ;get user HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 18 input command string EF52 [03] 25F5 654 bcs _main ;keep looking if ESC or ctl-C EF54 [04] C6040A 655 lda _inbuf ;check input buffer EF57 [03] 27F0 656 beq _main ;keep looking if empty (just CR entered) EF59 [02] A4DF 657 and #$DF ;turn to capital letter EF5B [03] 45F2E0 658 ldhx #_cmdtab ;point to command table EF5E [05] CDF62E 659 jsr _get_atbl ;get menu selection EF61 [03] 2403 660 bcc notfound ;valid menu item not selected EF63 [04] FD 661 jsr ,x ;found menu item, call corresponding routine EF64 [03] 20E3 662 bra _main ;get another command when processing done 663 notfound: EF66 [03] 45F3D8 664 ldhx #_ERR_MSG ;pointer to error string EF69 [05] CDF60A 665 jsr _puts ;print the string EF6C [03] 20DB 666 bra _main ;go get another command 667 668 ;*************************************************** ********* 669 ; _init_ustack After power up or download, checks for 670 ; valid user reset jump statement. If one exists, 671 ; then initialize user stack to go there on an rti 672 ;*************************************************** ********* 673 _init_ustack: EF6E [05] 0F0912 674 brclr 7,PortF,no_rst_vec ; "Mon Jumper" in place, we're in Monitor EF71 [03] 4503FB 675 ldhx #_user_stack-4 ; Read user stack address + rti frame EF74 [05] CDF149 676 jsr _save_sp ; Store address in stack_save EF77 [04] C6EF00 677 lda _user_reset ; Get address of user program reset EF7A [04] C703FE 678 sta _user_stack-1 ; and store in address field of stack frame EF7D [04] C6EF01 679 lda _user_reset+1 ; EF80 [04] C703FF 680 sta _user_stack 681 no_rst_vec: EF83 [04] 81 682 rts 683 684 ;*************************************************** ********* 685 ; _medit() Edit memory locations 686 ;*************************************************** ********* HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 19 687 _medit: EF84 [05] CDF677 688 jsr _first_hex EF87 [03] 252F 689 bcs end_medit 690 mexlp: EF89 [05] CDF586 691 jsr _crlf EF8C [05] CDF5AD 692 jsr _pword EF8F [02] F6 693 lda ,x EF90 [05] CDF5B9 694 jsr _pbyte_sp EF93 [05] CDF592 695 jsr _space EF96 [02] A602 696 lda #2 EF98 macro 697 pshhx EF98 [02] 89 698 PSHX EF99 [02] 8B 699 PSHH EF9A [05] CDF67E 700 jsr _gethex EF9D [04] C6040A 701 lda _inbuf EFA0 [03] 2508 702 bcs not_byte EFA2 [01] 9F 703 txa EFA3 [02] 8A 704 pulh EFA4 [02] 88 705 pulx EFA5 [02] F7 706 sta ,x EFA6 [02] AF01 707 aix #1 EFA8 [03] 20DF 708 bra mexlp 709 not_byte: EFAA macro 710 pulhx EFAA [02] 8A 711 PULH EFAB [02] 88 712 PULX EFAC [02] AF01 713 aix #1 EFAE [02] A120 714 cmp #SPACE EFB0 [03] 27D7 715 beq mexlp ; If nul entry (ENTER), go to next byte EFB2 [02] AFFE 716 aix #-2 EFB4 [02] A108 717 cmp #BS EFB6 [03] 27D1 718 beq mexlp ; If Backspace, go to previous byte 719 end_medit: EFB8 [04] 81 720 rts ; Else return 721 722 ;*************************************************** ********* 723 ; _dump() Dump Memory locations 724 ;*************************************************** ********* 725 _dump: EFB9 [05] CDF677 726 jsr _first_hex EFBC [03] 252E 727 bcs end_dump EFBE [01] 9F 728 txa ; Init even boundary EFBF [02] A4F0 729 and #$F0 EFC1 [01] 97 730 tax 731 prmem: EFC2 macro 732 pshhx EFC2 [02] 89 733 PSHX EFC3 [02] 8B 734 PSHH EFC4 [03] 45F312 735 ldhx #_HEADING EFC7 [05] CDF60A 736 jsr _puts EFCA macro 737 pulhx EFCA [02] 8A 738 PULH EFCB [02] 88 739 PULX 740 prmlp: HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 20 EFCC [01] 9F 741 txa EFCD [02] A40F 742 and #$0F EFCF [03] 260C 743 bne nxmem EFD1 [05] CDF586 744 jsr _crlf EFD4 macro 745 tha EFD4 [02] 8B 746 PSHH EFD5 [02] 86 747 PULA EFD6 [05] CDF5BE 748 jsr _pbyte EFD9 [01] 9F 749 txa EFDA [05] CDF58F 750 jsr _byte_sp 751 nxmem: EFDD [02] F6 752 lda ,x EFDE [05] CDF58F 753 jsr _byte_sp EFE1 [02] AF01 754 aix #1 EFE3 [01] 9F 755 txa EFE4 [01] 4D 756 tsta EFE5 [03] 26E5 757 bne prmlp 758 wt_end_dump: EFE7 [05] CDF5F6 759 jsr _do_again EFEA [03] 27D6 760 beq prmem 761 end_dump: EFEC [04] 81 762 rts 763 764 ;*************************************************** ********* 765 ;*************************************************** ********* 766 ; 767 ; D E B U G C O M M A N D S 768 ; 769 ;*************************************************** ********* 770 ;*************************************************** ********* 771 772 ;*************************************************** ********* 773 ; _fill() -- Fill Memory locations 774 ;*************************************************** ********* 775 _fill: EFED [05] CDF677 776 jsr _first_hex EFF0 [03] 252E 777 bcs end_fill EFF2 macro 778 pshhx EFF2 [02] 89 779 PSHX EFF3 [02] 8B 780 PSHH EFF4 [05] CDF66C 781 jsr _next_hex EFF7 [03] 2404 782 bcc get_val EFF9 macro 783 pulhx EFF9 [02] 8A 784 PULH EFFA [02] 88 785 PULX EFFB [03] 2023 786 bra end_fill 787 get_val: EFFD macro 788 tha EFFD [02] 8B 789 PSHH EFFE [02] 86 790 PULA EFFF [04] C70402 791 sta _tempx F002 [04] CF0403 792 stx _tempx+1 HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 21 F005 [05] CDF66C 793 jsr _next_hex F008 [01] 9F 794 txa F009 macro 795 pulhx F009 [02] 8A 796 PULH F00A [02] 88 797 PULX F00B [03] 2513 798 bcs end_fill 799 fill_lp: F00D [02] F7 800 sta ,x F00E [02] 87 801 psha F00F macro 802 tha F00F [02] 8B 803 PSHH F010 [02] 86 804 PULA F011 [04] C10402 805 cmp _tempx F014 [02] 86 806 pula F015 [03] 2605 807 bne nxt_fill F017 [04] C30403 808 cpx _tempx+1 F01A [03] 2704 809 beq end_fill 810 nxt_fill: F01C [02] AF01 811 aix #1 F01E [03] 20ED 812 bra fill_lp 813 end_fill: F020 [04] 81 814 rts 815 816 ;*************************************************** ********* 817 ; _pr_reg, _out_reg -- Outputs registers from user stack 818 ;*************************************************** ********* 819 _prreg: F021 [05] CDF586 820 jsr _crlf 821 _out_reg: F024 [03] 45F4BB 822 ldhx #SP_MSG F027 [05] CDF60A 823 jsr _puts F02A [05] CDF140 824 jsr _get_sp F02D [02] AFFF 825 aix #-1 F02F [05] CDF5AD 826 jsr _pword F032 macro 827 pshhx F032 [02] 89 828 PSHX F033 [02] 8B 829 PSHH F034 [03] 45F4BF 830 ldhx #CC_MSG 831 reg_lp: F037 [05] CDF60A 832 jsr _puts F03A [02] AF01 833 aix #1 F03C macro 834 pshhx F03C [02] 89 835 PSHX F03D [02] 8B 836 PSHH F03E [02] F6 837 lda ,x F03F [02] A13A 838 cmp #':' F041 [03] 2608 839 bne not_h_reg F043 [04] C60408 840 lda _h_save F046 [05] CDF5BE 841 jsr _pbyte F049 [03] 2016 842 bra nxt_reg 843 not_h_reg: F04B [04] 9EE603 844 lda 3,sp F04E macro 845 tah F04E [02] 87 846 PSHA F04F [02] 8A 847 PULH HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 22 F050 [04] 9EEE04 848 ldx 4,sp F053 [02] AF01 849 aix #1 F055 [02] F6 850 lda ,x F056 [05] CDF5BE 851 jsr _pbyte F059 macro 852 tha F059 [02] 8B 853 PSHH F05A [02] 86 854 PULA F05B [04] 9EE703 855 sta 3,sp F05E [04] 9EEF04 856 stx 4,sp 857 nxt_reg: F061 macro 858 pulhx F061 [02] 8A 859 PULH F062 [02] 88 860 PULX F063 [02] F6 861 lda ,x F064 [02] A145 862 cmp #'E' F066 [03] 26CF 863 bne reg_lp F068 macro 864 pulhx F068 [02] 8A 865 PULH F069 [02] 88 866 PULX F06A [04] 81 867 rts 868 869 ;*************************************************** ********* 870 ; _set_break -- Sets breakpoint 871 ;*************************************************** ********* 872 _set_break: F06B [05] CDF677 873 jsr _first_hex ; Gets breakpoint address F06E [03] 250A 874 bcs pr_brkpt F070 macro 875 tha ; store breakpoint so that it can be restored F070 [02] 8B 876 PSHH F071 [02] 86 877 PULA F072 [04] C70406 878 sta _last_break ; at next breakpoint when resuming F075 [04] CF0407 879 stx _last_break+1 F078 [04] AD1F 880 bsr _wt_break 881 pr_brkpt: F07A [03] 45F399 882 ldhx #_MSG_BREAK F07D [05] CDF60A 883 jsr _puts F080 [04] C6FE0E 884 lda brkscr F083 [03] 2A0B 885 bpl end_set_bp F085 [04] C6FE0C 886 lda brkh F088 macro 887 tah F088 [02] 87 888 PSHA F089 [02] 8A 889 PULH F08A [04] CEFE0D 890 ldx brkl F08D [05] CDF5AD 891 jsr _pword 892 end_set_bp: F090 [04] 81 893 rts 894 895 ;*************************************************** ********* 896 ; _restore_bk -- Restores break address to last set value 897 ;*************************************************** ********* HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 23 898 _restore_break: F091 [04] C60406 899 lda _last_break F094 macro 900 tah F094 [02] 87 901 PSHA F095 [02] 8A 902 PULH F096 [04] CE0407 903 ldx _last_break+1 904 905 ; _wt_break writes a break point at h:x 906 907 _wt_break: F099 [04] CFFE0D 908 stx brkl ; stores breakpoint F09C macro 909 tha F09C [02] 8B 910 PSHH F09D [02] 86 911 PULA F09E [04] C7FE0C 912 sta brkh F0A1 [02] A680 913 lda #$80 F0A3 [04] C7FE0E 914 sta brkscr ; enables breakpoint F0A6 [04] C7FE03 915 sta sbfcr ; Allows access to break status registers F0A9 [04] 81 916 rts 917 918 ;*************************************************** ********* 919 ; _clr_break -- Clears breakpoint 920 ;*************************************************** ********* 921 _clr_break: F0AA [01] 4F 922 clra ; disables breakpoint F0AB [04] C7FE0E 923 sta brkscr F0AE [04] 81 924 rts 925 926 ;*************************************************** ********* 927 ; _break_pt -- Routine to process breakpoint 928 ;*************************************************** ********* 929 _break_pt: F0AF [02] 9B 930 sei F0B0 [02] A680 931 lda #$80 F0B2 [04] C7FE03 932 sta sbfcr ; Allows access to break status registers F0B5 [04] C7FE0E 933 sta brkscr F0B8 macro 934 tha F0B8 [02] 8B 935 PSHH F0B9 [02] 86 936 PULA F0BA [04] C70408 937 sta _h_save ; Save h register F0BD [02] 95 938 tsx F0BE [05] CDF149 939 jsr _save_sp ; Save user stack pointer F0C1 [03] 450450 940 ldhx #_mon_stack+1 ; Transfer stack to monitor RAM F0C4 [02] 94 941 txs F0C5 [04] ADCA 942 bsr _restore_break ; restore breakpoint F0C7 [04] C60409 943 lda _state ; Check if this was a go from a breakpoint F0CA [02] A101 944 cmp #1 ; If so, we need to resume F0CC [03] 2607 945 bne not_resume HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 24 F0CE [01] 4F 946 clra ; Clear resume state F0CF [04] C70409 947 sta _state F0D2 [03] CCF18F 948 jmp _do_rti ; Resume from current breakpoint 949 not_resume: F0D5 [03] 45F399 950 ldhx #_MSG_BREAK ; Output breakpoint message F0D8 [05] CDF60A 951 jsr _puts F0DB [05] CDF024 952 jsr _out_reg ; Output registers F0DE [05] CDF12F 953 jsr _get_pc ; Get current user program counter F0E1 [05] CDF715 954 jsr _disasm_1x ; Disassemble where you are F0E4 [04] C60409 955 lda _state F0E7 [02] A102 956 cmp #2 ; Is it in single step mode? F0E9 [03] 2609 957 bne not_sstep ; If not, go back to prompt F0EB [05] CDF5F6 958 jsr _do_again ; If so, look for space to step next F0EE [03] 270B 959 beq _step_again ; If space, do next instruction F0F0 [01] 4F 960 clra ; If not, clear resume state F0F1 [04] C70409 961 sta _state ; and go back to prompt 962 not_sstep: F0F4 [03] CCEF49 963 jmp _main 964 965 ;*************************************************** ********* 966 ; _next -- Step one instruction 967 ;*************************************************** ********* 968 _next: F0F7 [04] AD22 969 bsr _is_stack_ok ; Only step if Stack is initialized F0F9 [03] 2533 970 bcs no_step ; WARNING: this is not a bullet-proof test! 971 _step_again: F0FB [04] AD08 972 bsr _break_next ; Set breakpoint to stop at next instruction F0FD [02] A602 973 lda #2 ; Sets single step state F0FF [04] C70409 974 sta _state F102 [03] CCF16B 975 jmp _go_stack ; 976 977 ;*************************************************** ********* 978 ; _break_next -- Set to break on next instruction Based on following: 979 ; - If current instruction is 2 or more bytes 980 ; setting the break in the 2nd byte will cause 981 ; the break to occur on the next instruction 982 ; - If one byte instruction, only jsr ,x and 983 ; jmp ,x will start at HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 25 next byte 984 ;*************************************************** ********* 985 _break_next: F105 [05] CDF12F 986 jsr _get_pc ; Get current user program counter F108 [02] F6 987 lda ,x F109 [02] AF01 988 aix #1 ; Check if instruction is a jmp ,x or jsr ,x F10B [02] A4FE 989 and #$FE F10D [02] A1FC 990 cmp #$FC F10F [03] 2607 991 bne not_jx F111 [04] AD24 992 bsr _get_hx F113 [02] F6 993 lda ,x ; If it is a jmp ,x or jsr ,x F114 [03] EE01 994 ldx 1,x ; Then set break at address pointed to by x-reg F116 macro 995 tah F116 [02] 87 996 PSHA F117 [02] 8A 997 PULH 998 not_jx: F118 [03] CCF099 999 jmp _wt_break 1000 1001 ;*************************************************** ********* 1002 ; _is_stack_ok returns carry clear if ok, set if not, 1003 ; 1004 ;*************************************************** ********* 1005 _is_stack_ok: F11B [04] C60404 1006 lda _stack_save ; Check that user SP is valid F11E [03] 2706 1007 beq ck_ss_low F120 [02] A101 1008 cmp #1 F122 [03] 2609 1009 bne stk_not_ok F124 [03] 2005 1010 bra stk_ok 1011 ck_ss_low: F126 [04] C60405 1012 lda _stack_save+1 F129 [03] 2702 1013 beq stk_not_ok 1014 stk_ok: F12B [01] 98 1015 clc F12C [04] 81 1016 rts 1017 stk_not_ok: F12D [01] 99 1018 sec 1019 no_step: 1020 end_go: F12E [04] 81 1021 rts 1022 1023 ;*************************************************** ********* 1024 ; _get_pc Gets user PC off of user stack, returned in h:x reg 1025 ;*************************************************** ********* 1026 _get_pc: F12F [04] AD0F 1027 bsr _get_sp F131 [03] E603 1028 lda 3,x HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 26 F133 [03] EE04 1029 ldx 4,x F135 [03] 200F 1030 bra done_get 1031 1032 ;*************************************************** ********* 1033 ; _get_hx Gets user h:x reg, gets x-reg off of stack and 1034 ; h reg from _h_save. Returns in h:x reg 1035 ;*************************************************** ********* 1036 _get_hx: F137 [04] AD07 1037 bsr _get_sp F139 [03] EE02 1038 ldx 2,x F13B [04] C60408 1039 lda _h_save F13E [03] 2006 1040 bra done_get 1041 1042 ;*************************************************** ********* 1043 ; _get_sp Gets user stack pointer from +stack_save 1044 ; Returns in h:x reg 1045 ;*************************************************** ********* 1046 _get_sp: F140 [04] C60404 1047 lda _stack_save F143 [04] CE0405 1048 ldx _stack_save+1 1049 done_get: F146 macro 1050 tah F146 [02] 87 1051 PSHA F147 [02] 8A 1052 PULH F148 [04] 81 1053 rts 1054 1055 ;*************************************************** ********* 1056 ; _save_sp Saves user stack pointer in stack_save 1057 ; Passed in h:x reg 1058 ;*************************************************** ********* 1059 _save_sp: F149 macro 1060 tha F149 [02] 8B 1061 PSHH F14A [02] 86 1062 PULA F14B [04] C70404 1063 sta _stack_save ; Store address in stack_save F14E [04] CF0405 1064 stx _stack_save+1 F151 [04] 81 1065 rts 1066 1067 ;*************************************************** ********* 1068 ; go(*x-reg) Execute program at X-reg 1069 ;*************************************************** ********* 1070 _go: F152 [05] CDF677 1071 jsr _first_hex F155 [03] 2510 1072 bcs chk_stack_add F157 macro 1073 tha HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 27 F157 [02] 8B 1074 PSHH F158 [02] 86 1075 PULA F159 [04] CF0402 1076 stx _tempx F15C [03] 450400 1077 ldhx #_user_stack+1 F15F [02] 94 1078 txs F160 macro 1079 tah F160 [02] 87 1080 PSHA F161 [02] 8A 1081 PULH F162 [04] CE0402 1082 ldx _tempx F165 [02] 9A 1083 cli F166 [02] FC 1084 jmp ,x ; Call user prog,x 1085 chk_stack_add: F167 [04] ADB2 1086 bsr _is_stack_ok F169 [03] 25C3 1087 bcs end_go 1088 _go_stack: F16B [04] C6FE0E 1089 lda brkscr F16E [03] 2A1F 1090 bpl _do_rti F170 [05] CDF12F 1091 jsr _get_pc ; Get current user program counter F173 [04] C3FE0D 1092 cpx brkl ; compares breakpoint address to current F176 [03] 2617 1093 bne _do_rti F178 macro 1094 tha F178 [02] 8B 1095 PSHH F179 [02] 86 1096 PULA F17A [04] C1FE0C 1097 cmp brkh F17D [03] 2610 1098 bne _do_rti F17F [02] A601 1099 lda #1 ; If currently at breakpoint, set _state to 1 F181 [04] C70409 1100 sta _state ; to indicate to continue from next break F184 macro 1101 tha ; and store breakpoin t to be restored F184 [02] 8B 1102 PSHH F185 [02] 86 1103 PULA F186 [04] C70406 1104 sta _last_break ; at next breakpoint when resuming F189 [04] CF0407 1105 stx _last_break+1 F18C [05] CDF105 1106 jsr _break_next ; and set break at next instruction 1107 _do_rti: F18F [04] ADAF 1108 bsr _get_sp ; If user SP is valid, set SP to user SP and do RTI F191 [02] 94 1109 txs F192 [04] C60408 1110 lda _h_save F195 macro 1111 tah F195 [02] 87 1112 PSHA F196 [02] 8A 1113 PULH F197 [07] 80 1114 rti 1115 1116 ;*************************************************** ********* 1117 ; Prints Help message 1118 ;*************************************************** ********* 1119 _help: F198 [03] 45F3A3 1120 ldhx #_PWR_MSG F19B [05] CDF60A 1121 jsr _puts HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 28 F19E [03] 45F3DD 1122 ldhx #_HELPLIST F1A1 [05] CDF60A 1123 jsr _puts F1A4 [04] 81 1124 rts 1125 1126 ;*************************************************** ********* 1127 ; Copy Flash Mass Erase algorithm into RAM and execute. 1128 ;*************************************************** ********* 1129 1130 ; ram_exec equ $200-STACK_ALLOC-ProgramRamSiz e+1 ; executable RAM 1131 F1A5 1132 ram_exec equ $19A 1133 1134 _do_mass_erase: F1A5 [03] 45003B 1135 ldhx #EraseRamSize ; initialize pointer 1136 BootErase1: F1A8 [04] D6F268 1137 lda MassErase-1,x ; get program from Flash F1AB [04] D70199 1138 sta ram_exec-1,x ; copy into RAM F1AE [03] 5BF8 1139 dbnzx BootErase1 ; decrement pointer and loop back until done F1B0 [05] CD019A 1140 jsr ram_exec ; execute Flash Mass Erase algorithm from RAM 1141 BootDone: F1B3 [05] CDEF6E 1142 jsr _init_ustack ; initialize user stack F1B6 [04] 81 1143 rts 1144 1145 ;--------------------------------------------------- ---------------- 1146 ; Check for Program Flash command. 1147 1148 _do_dnload: 1149 ; Copy Program Flash algorithm into RAM and execute. 1150 F1B7 [03] 450047 1151 ldhx #ProgramRamSize ; initialize pointer 1152 BootProg: F1BA [04] D6F298 1153 lda _delay-1,x ; get program from Flash F1BD [04] D70199 1154 sta ram_exec-1,x ; copy into RAM F1C0 [03] 5BF8 1155 dbnzx BootProg ; decrement pointer and loop back until done F1C2 [03] 45F380 1156 ldhx #_MSG_WAITING ; point to waiting message F1C5 [05] CDF60A 1157 jsr _puts ; output it 1158 1159 ; Get S-Record from host. 1160 BootProg1: F1C8 [04] C7FFFF 1161 sta copctl ; clear the COP counter F1CB [02] 95 1162 tsx ; get the Stack Pointer F1CC [04] 3551 1163 sthx _temp_sp ; save it temporarily F1CE [02] A7DC 1164 ais #-36T ; allocate stack HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 29 space for data F1D0 [05] CDF211 1165 jsr GetSRec ; get an S-Record F1D3 [03] 2620 1166 bne BootProg3 ; indicate error if S-Record is invalid F1D5 [02] 86 1167 pula ; get S-Record type F1D6 [02] A139 1168 cmp #'9' ; check for end record type F1D8 [03] 270B 1169 beq BootProg2 ; indicate operation complete F1DA [02] A131 1170 cmp #'1' ; check for data record type F1DC [03] 2617 1171 bne BootProg3 ; indicate error if S-Record is invalid 1172 1173 ; Program Flash. 1174 F1DE [05] CD01A5 1175 jsr {ram_exec+ProgramRam} ; execute Program Flash alg from RAM F1E1 [02] A723 1176 ais #35T ; deallocate stack space F1E3 [03] 20E3 1177 bra BootProg1 ; loop bacl for next S-Record 1178 1179 BootProg2: F1E5 [02] A723 1180 ais #35T ; deallocate stack space F1E7 [05] 0B16C9 1181 brclr SCRF,scs1,BootDone ; skip if SCI receiver is empty F1EA [05] CDF5D7 1182 jsr _getchne ; else, clear last ASCII carriage 1183 ; return from the SCI F1ED [05] 0B16C3 1184 brclr SCRF,scs1,BootDone ; skip if SCI receiver is empty F1F0 [05] CDF5D7 1185 jsr _getchne ; else, clear last LF from the SCI F1F3 [03] 20BE 1186 bra BootDone ; indicate operation complete 1187 1188 BootProg3: F1F5 [02] A724 1189 ais #36T ; deallocate stack space 1190 1191 ; Respond to error situations. 1192 F1F7 [03] 45F38F 1193 ldhx #_MSG_ERROR ; point to error message 1194 Boot4: F1FA [05] CDF60A 1195 jsr _puts ; output it F1FD [03] CCEF3B 1196 jmp _boot ; jump back to the top 1197 1198 ;*************************************************** ***************** 1199 ; CGM PLL Bus Frequency Change Subroutine 1200 ; 1201 ; This subroutine will program the CGM PLL to change the bus frequency HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 30 1202 ; from that of the 4.915 MHz xtal to about 8 MHz 1203 ;*************************************************** ***************** 1204 PLLset: F200 [04] 191C 1205 bclr BCS,pctl ; select external reference as base clock F202 [04] 1B1C 1206 bclr PLLON,pctl ; turn off PLL F204 [04] 6E771E 1207 mov #$77,PPG ; set up PLL Programming Register F207 [04] 1E1D 1208 bset AUTO,pbwc ; enable automatic bandwidth control F209 [04] 1A1C 1209 bset PLLON,pctl ; turn on PLL 1210 PLLwait: F20B [05] 0D1DFD 1211 brclr LOCK,pbwc,PLLwait ; wait for PLL to lock F20E [04] 181C 1212 bset BCS,pctl ; select VCO as base clock F210 [04] 81 1213 rts ; return 1214 1215 1216 ;*************************************************** ***************** 1217 ; GetSRec Subroutine 1218 ; 1219 ; This subroutine will retrieve data in S19 record format via the SCI. 1220 ; 1221 ; Calling convention: 1222 ; 1223 ; ais #-buffer_length 1224 ; jsr GetSRec 1225 ; 1226 ; Returns: CCRZ= 1 if valid S-Record retrieved. Otherwise, CCRZ= 0. 1227 ; S-Record Type at SP+1 (1 byte) 1228 ; S-Record Size at SP+2 (1 byte) 1229 ; S-Record Address at SP+3 (2 bytes) 1230 ; S-Record Data at SP+5 (up to 32 bytes, typically) 1231 ; 1232 ; | | <-sp (after local space allocation) 1233 ; H:X-> | SRecCount | 1234 ; | SRecChkSum | <-sp (when called) 1235 ; | ReturnAddr msb | 1236 ; | ReturnAddr lsb | <-sp (upon return) 1237 ; | SRecType | 1238 ; | SRecSize | 1239 ; H:X-> | SRecAddr msb | 1240 ; | SRecAddr lsb | 1241 ; | SRecData 00 | 1242 ; | SRecData 01 | etc.. 1243 ; 1244 ; Changes: ACC, H:X 1245 ;*************************************************** HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 31 ***************** F211 1246 SRecCount equ 1 ; stack pointer offset for S-Record Counter (local) F211 1247 SRecChkSum equ 2 ; stack pointer offset for S-Record Check Sum (local) F211 1248 SRecType equ 5 ; stack pointer offset for S-Record Type F211 1249 SRecSize equ 6 ; stack pointer offset for S-Record Size F211 1250 SRecAddr equ 7 ; stack pointer offset for S-Record Address F211 1251 SRedData equ 8 ; stack pointer offset for S-Record Data 1252 1253 GetSRec: F211 [02] A7FE 1254 ais #-2 ; allocate local variable space F213 [04] 9E6F06 1255 clr SRecSize,sp ; initialize S-Record size 1256 GetSRec1: F216 [05] CDF5D7 1257 jsr _getchne ; get a character from the SCI F219 1258 #if HYPERTERM F219 1259 #elseif F219 [05] CDF59C 1260 jsr _putch ; echo it back F21C 1261 #endif F21C [02] A10D 1262 cmp #CR ; check for ASCII carriage return F21E [03] 2605 1263 bne GetSRec1a ; just loop back if so F220 [02] A60A 1264 lda #LF ; get ASCII line feed F222 1265 #if HYPERTERM F222 1266 #elseif F222 [05] CDF59C 1267 jsr _putch ; echo it back F225 1268 #endif 1269 GetSRec1a: F225 [02] A153 1270 cmp #'S' ; check for start of record character F227 [03] 26ED 1271 bne GetSRec1 ; loop back if not F229 [05] CDF5D7 1272 jsr _getchne ; else, get next character from the SCI F22C 1273 #if HYPERTERM F22C 1274 #elseif F22C [05] CDF59C 1275 jsr _putch ; echo it back F22F 1276 #endif F22F [02] A130 1277 cmp #'0' ; check for header record type F231 [03] 27E3 1278 beq GetSRec1 ; loop back if so F233 [02] A139 1279 cmp #'9' ; else, check for end record type F235 [03] 2704 1280 beq GetSRec2 ; continue if so F237 [02] A131 1281 cmp #'1' ; else, check for data record type F239 [03] 26DB 1282 bne GetSRec1 ; loop back if not 1283 GetSRec2: F23B [04] 9EE705 1284 sta SRecType,sp ; save S-Record type F23E [05] CDF60E 1285 jsr GetHexByte ; get the S-Record length F241 [03] 2623 1286 bne GetSRec4 ; exit if not a valid HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 32 hex byte F243 [04] 9EE701 1287 sta SRecCount,sp ; initialize S-Record counter F246 [04] 9EE702 1288 sta SRecChkSum,sp ; initialize S-Record check sum F249 [02] A003 1289 sub #3 ; adjust for address and checksum F24B [04] 9EE706 1290 sta SRecSize,sp ; save S-Record size F24E [02] 95 1291 tsx ; use H:X as data stack frame pointer F24F [02] AF06 1292 aix #(SRecAddr-1) ; adjust so pointer starts at S-Record Address 1293 GetSRec3: F251 [05] CDF60E 1294 jsr GetHexByte ; get next S-Record hex byte F254 [03] 2610 1295 bne GetSRec4 ; exit if not a valid hex byte F256 [02] F7 1296 sta ,x ; save data in stack frame F257 [04] 9EEB02 1297 add SRecChkSum,sp ; add data to check sum F25A [04] 9EE702 1298 sta SRecChkSum,sp ; save new check sum F25D [02] AF01 1299 aix #1 ; move data stack frame pointer F25F [06] 9E6B01EE 1300 dbnz SRecCount,sp,GetSRec3 ; loop back until all data received F263 [05] 9E6C02 1301 inc SRecChkSum,sp ; final calc zeros check sum if it's okay 1302 GetSRec4: F266 [02] A702 1303 ais #2 ; deallocate local variables F268 [04] 81 1304 rts ; return 1305 1306 ;*************************************************** *********************** 1307 ; Flash Mass Erase Subroutine 1308 ; This subroutine performs multiple Page Erase operations in order 1309 ; to completely erase the application space Flash memory. 1310 ; This subroutine is copied into and executed from RAM. 1311 ;*************************************************** ***************** 1312 MassErase: F269 [03] 458000 1313 ldhx #rom_start ; initialize pointer to start of Flash memory 1314 1315 MassErase1: 1316 ; Set ERASE, read the Flash Block Protect Register and write any 1317 ; data into Flash page. F26C [02] A602 1318 lda #ERASE ; set ERASE control bit F26E [04] C7FE08 1319 sta flcr ; in Flash Control Register F271 [04] C6FF7E 1320 lda flbpr ; read from Flash Block Protect Register HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 33 F274 [02] F7 1321 sta ,x ; write any data to address within page 1322 1323 ; Wait for >10us, then set HVEN. F275 [02] A601 1324 lda #1 ; wait F277 [04] AD20 1325 bsr _delay ; for 11.7us F279 [02] A60A 1326 lda #(ERASE|HVEN) ; set HVEN control bit F27B [04] C7FE08 1327 sta flcr ; in Flash Control Register 1328 1329 ; Wait for >1ms, then clear ERASE. F27E [02] A664 1330 lda #100T ; wait F280 [04] AD17 1331 bsr _delay ; for 1.005ms F282 [02] A608 1332 lda #HVEN ; clear ERASE control bit F284 [04] C7FE08 1333 sta flcr ; in Flash Control Register 1334 1335 TestLabel: 1336 ; Wait for >5us, then clear HVEN. F287 [02] A601 1337 lda #1 ; wait F289 [04] AD0E 1338 bsr _delay ; for 11.7us F28B [01] 4F 1339 clra ; clear HVEN control bit F28C [04] C7FE08 1340 sta flcr ; in Flash Control Register 1341 1342 ; Advance pointer and repeat until finished. F28F [02] AF40 1343 aix #{flash_page/2} ; add half of Flash Erase Page size twice, F291 [02] AF40 1344 aix #{flash_page/2} ; since it's 128 bytes for GP32 F293 [03] 65E000 1345 cphx #boot_start ; check if finished F296 [03] 26D4 1346 bne MassErase1 ; loop back if not 1347 F298 [04] 81 1348 rts ; return 1349 1350 ;*************************************************** ***************** 1351 ; delay Subroutine 1352 ; 1353 ; This subroutine performs a simple software delay loop based upon 1354 ; the value passed in ACC. 1355 ; The following timing calculation applies: 1356 ; 1357 ; delay = ((ACC * 74) + 12) (tcyc) 1358 ; If A=1 1359 ; then delay = 11.7us at 114.545ns/cycle 1360 ; 1361 ;*************************************************** ***************** 1362 _delay: F299 [02] 87 1363 psha ; [2] save delay parameter temporarily 1364 delay1: F29A [02] A666 1365 lda #102T ; [2] initialize 5us HCmon_v2.asm Assembled with CASM08Z 6/24/2003 11:28:35 PM PAGE 34 loop counter 1366 ; (repeat for timing) 1367 delay2: F29C [03] 4BFE 1368 dbnza delay2 ; [3] decrement inner delay loop counter F29E [06] 9E6B01F8 1369 dbnz 1,sp,delay1 ; [6] decrement outer delay loop counter F2A2 [02] 86 1370 pula ; [2] deallocate local variable F2A3 [04] 81 1371 rts ; [4] return 1372 F2A4 1373 EraseRamSize equ (*-MassErase) F2A4 1374 ProgramRam equ (*-_delay) 1375 1376 ;*************************************************** ***************** 1377 ; Flash Program Subroutine 1378 ; 1379 ; This subroutine controls the Flash programmi ng sequence. A stack 1380 ; frame data block is passed to it in the format shown below. 1381 ; This subroutine is copied into and executed from RAM. 1382 ; 1383 ; | | <-sp (when called) 1384 ; | ReturnAddr msb | 1385 ; | ReturnAddr lsb | <-sp (upon return) 1386 ; | SRecSize | 1387 ; | SRecAddr msb | 1388 ; | SRecAddr lsb | 1389 ; | SRecData 00 | 1390 ; | SRecData 01 | etc.. 1391 ;*************************************************** ***************** 1392 FlashProgram: F2A4 [02] 95 1393 tsx ; get the Stack