HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 1 1 ; ************************************************** ************************* 2 ; * 3 ; HC908 Debug Monitor V1.0 * 4 ; George Heron, N2APB * 5 ; 12/2002 * 6 ; * 7 ; This program is a simple, low-level debug monitor developed to support * 8 ; the projects based on the "HC908 Daughtercard" project described * 9 ; in QRP Homebrewer magazine (published by the NJQRP Club), in QRP * 10 ; Quarterly magazine (published by QRP ARCI), and on the website of the * 11 ; New Jersey QRP Club (www.njqrp.org) * 12 ; * 13 ; The operator interfaces to the HC908 Debug Monitor by means of a dumb * 14 ; terminal connected to the RS-232 serial port of the MPU daughtercard. * 15 ; Through the Monitor's command/response structure, the operator may edit * 16 ; memory amd MPU registers, set and reset breakpoint s, "go" or single step * 17 ; from any executable location in the loaded program, load S record files * 18 ; sent by the terminal, program Flash memory from the downloaded S records, * 19 ; and read input ports and set output ports. * 20 ; * 21 ; The HC908 Debug Monitor is programmed into all HC908 Daughtercards after * 22 ; manufacture. In some instances, another software program may also be * 23 ; programmed in the HC908 Daughtercard at time of manufacture, providing * 24 ; the customer with one of a growing number of software applications for * 25 ; this product (e.g., the Digital Breadboard, the Antenna Analyzer, HC908 * 26 ; Commander, the HC908 Digital VFO and others). * 27 ; * 28 ; As mentioned, the HC908 Daughtercard and its debug monitor provides the * 29 ; user with an ability to program the permament and nonvolatile "flash" * HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 2 30 ; memory directly from downloaded "S records". An S record file is a common * 31 ; format for the assembled or compiled 68HC908 MPU binary code, as * 32 ; used in most Motorola-based processors and tools. Thus, when a user * 33 ; wishes to load a program other than what arrived on his HC908 * 34 ; Daughtercard, he may download any of the available S record files from the* 35 ; project's Internet website and "burn" the program into the MPU's flash * 36 ; memory, thus making the program permanent and available for his use. In * 37 ; this way, the user is able to change the HC908 Daughtercard's * 38 ; "personality" without any other tools than a terminal program connected * 39 ; to the Daughtercard on its serial port. * 40 ; * 41 ; Most "dumb terminals" may be used to communicate with the HC908 Debug * 42 ; Monitor. Examples of such programs include HyperTerminal, Red Ryder, * 43 ; ProComm and PCPlus. However, a useful, public domain (freeware) terminal * 44 ; program called "Tera Term" is also available to run on Microsoft Windows * 45 ; platforms. Tera Term has a convenient scripting ability that can be * 46 ; invoked to send an S record file (like a new software program) to your * 47 ; HC908 Daughtercard for flash programming by the Monitor. The Tera Term * 48 ; terminal program and its S record transfer script are provided on the * 49 ; HC908 project website for users to download and use on their systems. * 50 ; * 51 ; There are many more features and details concernin g the use of the HC908 * 52 ; Debug Monitor on the HC908 Daughtercard-based projects. Please refer to * 53 ; written documentation provided with the Monitor and Daughtercard for the * 54 ; latest and authoritative information concerning capabilities and use. * 55 ; * 56 ; Questions may be addressed to me by email and I'll do my best to help out.* 57 ; * 58 ; George Heron, N2APB * HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 3 59 ; email: n2apb@amsat.org * 60 ; * 61 ; ************************************************** ************************* 62 ; GNU Public License * 63 ; * 64 ; This program is free software; you can redistrib ute it and/or modify * 65 ; it under the terms of the GNU General Public License as published by * 66 ; the Free Software Foundation; either version 2 of the License, or * 67 ; (at your option) any later version. * 68 ; * 69 ; This program is distributed in the hope that it will be useful, * 70 ; but WITHOUT ANY WARRANTY; without even the implied warranty of * 71 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 72 ; GNU General Public License for more details. * 73 ; * 74 ; You should have received a copy of the GNU General Public License * 75 ; along with this program; if not, write to the Free Software * 76 ; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * 77 ; * 78 ; See license.txt file for details * 79 ; * 80 ;*************************************************** ************************* 81 ; Credits: 82 ; * 83 ; Major portions of this program were adapted from the Pony 68HC908 Debug * 84 ; Monitor V1.4 by Larry Bateman. Copyright (c) 2000, L3 Systems. * 85 ; * 86 ; Portions borrowed from Motorola's "MC68HC908GP32 User Bootloader", * 87 ; Copyright (c) Motorola 2000. Written by DGJ Klotz Rev ES 1.0 26-Feb-00 * 88 ; HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 4 * 89 ; ************************************************** ************************* 90 0000 91 $BASE 10T 92 0000 93 include "../AB_REGS.INC" ; MC68HC908GP32 register defimitions 94 ; 68HC908AB32 Equates 95 0000 96 PTA EQU $0000 ; Ports and data direction 0000 97 PORTA EQU $0000 0000 98 PTB EQU $0001 0000 99 PORTB EQU $0001 0000 100 PTC EQU $0002 0000 101 PORTC EQU $0002 0000 102 PTD EQU $0003 0000 103 PORTD EQU $0003 0000 104 DDRA EQU $0004 0000 105 DDRB EQU $0005 0000 106 DDRC EQU $0006 0000 107 DDRD EQU $0007 108 0000 109 PTE EQU $0008 0000 110 PORTE EQU $0008 0000 111 PTF EQU $0009 0000 112 PORTF EQU $0009 0000 113 PTG EQU $000A 0000 114 PORTG EQU $000A 0000 115 PTH EQU $000B 0000 116 PORTH EQU $000B 117 0000 118 DDRE EQU $000C 0000 119 DDRF EQU $000D 0000 120 DDRG EQU $000E 0000 121 DDRH EQU $000F 122 123 ;* Serial Peripheral Interface Module (SPI) ******************************** 124 0000 125 spcr equ $10 ; SPI Control Register 0000 126 SPRIE equ 7 ; SPI receiver interrupt enable bit 0000 127 SPMSTR equ 5 ; SPI master bit 0000 128 CPOL equ 4 ; clock polarity bit 0000 129 CPHA equ 3 ; clock phase bit 0000 130 SPWOM equ 2 ; SPI wired-or mode bit 0000 131 SPE equ 1 ; SPI enable 0000 132 SPTIE equ 0 ; SPI transmit interrupt enable 133 0000 134 spscr equ $11 ; SPI Status and Control Register HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 5 0000 135 SPRF equ 7 ; SPI receiver full bit 0000 136 ERRIE equ 6 ; error interrupt enable bit 0000 137 OVRF equ 5 ; overflow bit 0000 138 MODF equ 4 ; mode fault bit 0000 139 SPTE equ 3 ; SPI transmitter empty bit 0000 140 MODFEN equ 2 ; mode fault enable bit 0000 141 SPR1 equ 1 ; SPI baud rate 0000 142 SPR0 equ 0 ; select bits 143 0000 144 spdr equ $12 ; SPI Data Register 145 146 147 ;* Serial Communications Interface (SCI) ********* ************************* 148 0000 149 scc1 equ $13 ; SCI Control Register 1 0000 150 LOOPS equ 7 ; loop mode select bit 0000 151 ENSCI equ 6 ; enable SCI bit 0000 152 TXINV equ 5 ; transmit inversion bit 0000 153 M equ 4 ; mode bit 0000 154 WAKE equ 3 ; wakeup condition bit 0000 155 ILTY equ 2 ; idle line type bit 0000 156 PEN equ 1 ; parity enable bit 0000 157 PTY equ 0 ; parity bit 158 0000 159 scc2 equ $14 ; SCI Control Register 2 0000 160 SCTIE equ 7 ; SCI transmit interrupt enable bit 0000 161 TCIE equ 6 ; transmissi on complete int enable bit 0000 162 SCRIE equ 5 ; SCI receive interrupt enable bit 0000 163 ILIE equ 4 ; idle line interrupt enable bit 0000 164 TE equ 3 ; transmitte r enable bit 0000 165 RE equ 2 ; receiver enable bit 0000 166 RWU equ 1 ; receiver wakeup bit 0000 167 SBK equ 0 ; send HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 6 break bit 168 0000 169 scc3 equ $15 ; SCI Control Register 3 0000 170 R8 equ 7 ; received bit 8 0000 171 T8 equ 6 ; transmitte d bit 8 0000 172 ORIE equ 3 ; receiver overrun interrupt enable bit 0000 173 NEIE equ 2 ; receiver noise error int enable bit 0000 174 FEIE equ 1 ; receiver framing error int enable bit 0000 175 PEIE equ 0 ; receiver parity error int enable bit 176 0000 177 scs1 equ $16 ; SCI Status Register 1 0000 178 SCTE equ 7 ; SCI transmitter empty bit 0000 179 TC equ 6 ; transmissi on complete bit 0000 180 SCRF equ 5 ; SCI receiver full bit 0000 181 IDLE equ 4 ; receiver idle bit 0000 182 OR equ 3 ; receiver overrun bit 0000 183 NF equ 2 ; receiver noise flag bit 0000 184 FE equ 1 ; receiver framing error bit 0000 185 PE equ 0 ; receiver parity error bit 186 0000 187 scs2 equ $17 ; SCI Status Register 2 0000 188 BKF equ 1 ; break flag bit 0000 189 RPF equ 0 ; reception in progress flag bit 190 ; 0000 191 scdr equ $18 ; SCI Data Register 0000 192 scbr equ $19 ; SCI Baud Rate Register 193 194 195 ;* External Interrupt (IRQ) ********************** ************************* 196 0000 197 intscr equ $1D ; IRQ Status and Control Register 0000 198 IRQF equ 3 ; IRQ flag bit 0000 199 ACK equ 2 ; IRQ interrupt request acknowledge bit HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 7 0000 200 IMASK equ 1 ; IRQ interrupt mask bit 0000 201 MODE equ 0 ; IRQ edge/level select bit 202 0000 203 ISCR EQU $001A 204 205 206 ;* Keyboard Interrupt Module (KBI) *************** ************************* 207 0000 208 intkbscr equ $1B ; Keyboard Status and Control Register 0000 209 KBSCR EQU $001B 0000 210 KEYF equ 3 ; keyboard flag bit 0000 211 ACKK equ 2 ; keyboard acknowledge bit 0000 212 IMASKK equ 1 ; keyboard interrupt mask bit 0000 213 MODEK equ 0 ; keyboard triggering sensitivity bit 214 ; 0000 215 intkbier equ $21 ; Keyboard Interrupt Enable Register 0000 216 KBICR EQU $0021 0000 217 KBIE4 equ 4 0000 218 KBIE3 equ 3 0000 219 KBIE2 equ 2 0000 220 KBIE1 equ 1 0000 221 KBIE0 equ 0 222 223 224 ;* Clock Generator Module (CGMC) ***************** ************************* 225 0000 226 pctl equ $1C ; PLL Control Register 0000 227 PLLIE equ 7 ; PLL interrupt enable bit 0000 228 PLLF equ 6 ; PLL interrupt flag bit 0000 229 PLLON equ 5 ; PLL on bit 0000 230 BCS equ 4 ; base clock select bit 231 ; 0000 232 pbwc equ $1D ; PLL Bandwidth Control Register 0000 233 AUTO equ 7 ; automatic bandwidth control bit 0000 234 LOCK equ 6 ; lock indicator bit 0000 235 ACQ equ 5 ; acquisitio n mode bit 236 0000 237 PPG equ $001E ; PLL Programmin g Register 238 ; Multiplier HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 8 Select bits [7:4] 239 ; VCO Frequency Multiplier bit [3:0] 240 241 ;* Configuration Registers (CONFIG) ************** ************************* 242 0000 243 CONFIG EQU $001F ; System configuration 0000 244 CONFIG1 EQU $001F 0000 245 CONFIG2 EQU $003F 246 0000 247 TASC EQU $0020 ; Timer A 0000 248 TACNTH EQU $0022 0000 249 TACNTL EQU $0023 0000 250 TAMODH EQU $0024 0000 251 TAMODL EQU $0025 0000 252 TASC0 EQU $0026 0000 253 TACH0H EQU $0027 0000 254 TACH0L EQU $0028 0000 255 TASC1 EQU $0029 0000 256 TACH1H EQU $002A 0000 257 TACH1L EQU $002B 0000 258 TASC2 EQU $002C 0000 259 TACH2H EQU $002D 0000 260 TACH2L EQU $002E 0000 261 TASC3 EQU $002F 0000 262 TACH3H EQU $0030 0000 263 TACH3L EQU $0031 264 0000 265 TBSC EQU $0041 ; Timer B 0000 266 TBCNTH EQU $0042 0000 267 TBCNTL EQU $0043 0000 268 TBMODH EQU $0044 0000 269 TBMODL EQU $0045 0000 270 TBSC0 EQU $0046 0000 271 TBCH0H EQU $0047 0000 272 TBCH0L EQU $0048 0000 273 TBSC1 EQU $0049 0000 274 TBCH1H EQU $004A 0000 275 TBCH1L EQU $004B 0000 276 TBSC2 EQU $0032 0000 277 TBCH2H EQU $0033 0000 278 TBCH2L EQU $0034 0000 279 TBSC3 EQU $0035 0000 280 TBCH3H EQU $0036 0000 281 TBCH3L EQU $0037 282 0000 283 TSC EQU $004B ; Timer 0000 284 TCNTH EQU $004C 0000 285 TCNTL EQU $004D 0000 286 TMODH EQU $004E 0000 287 TMODL EQU $004F 288 289 290 291 ;* Analog-to-Digital Converter (ADC) ************* ************************* 292 HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 9 0000 293 adscr equ $38 ; ADC Status and Control Register 0000 294 COCO equ 7 ; conversion s complete flag 0000 295 AIEN equ 6 ; ADC interrupt enable bit 0000 296 ADCO equ 5 ; ADC continuous conversion bit 0000 297 ADCH4 equ 4 ; \ 0000 298 ADCH3 equ 3 ; \ 0000 299 ADCH2 equ 2 ; ADC channel select bits 0000 300 ADCH1 equ 1 ; / 0000 301 ADCH0 equ 0 ; / 302 0000 303 adr equ $39 ; ADC Data Register 304 0000 305 adclk equ $3A ; ADC Clock Register 0000 306 ADIV2 equ 7 ; \ 0000 307 ADIV1 equ 6 ; ADC clock prescaler bits 0000 308 ADIV0 equ 5 ; / 0000 309 ADICLK equ 4 ; ADC input clock select bit 310 311 ;* Pullup Registers ******************************* ******* 312 0000 313 PTDPUE EQU $003D 0000 314 PTFPUE EQU $003E 0000 315 PRTFPU EQU $003E 316 317 ;* System Integration Module (SIM) *************** ************************* 318 0000 319 sbsr equ $FE00 ; SIM Break Status Register 0000 320 SBSW equ 1 ; SIM break stop/wait 321 0000 322 srsr equ $FE01 ; SIM Reset Status Register 0000 323 POR equ 7 ; power-on reset bit 0000 324 PIN equ 6 ; external reset bit 0000 325 COP equ 5 ; COP reset bit 0000 326 ILOP equ 4 ; illegal opcode reset bit 0000 327 ILAD equ 3 ; illegal opcode address reset bit 328 ;MODRST equ 2 ; monitor mode entry module reset bit 0000 329 LVI equ 1 ; LVI reset bit HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 10 330 0000 331 sbfcr equ $FE03 ; SIM Break Flag Control Register 0000 332 BCFE equ 7 ; break clear flag enable bit 333 334 ;* Flash Memory ********************************** ************************* 335 0000 336 flcr equ $FE08 ; Flash Control Register 0000 337 HVEN equ %00001000 ; high-voltage enable bit mask 0000 338 MASS equ %00000100 ; mass erase control bit mask 0000 339 ERASE equ %00000010 ; erase control bit mask 0000 340 PGM equ %00000001 ; program control bit mask 341 0000 342 flbpr equ $FF7E ; Flash Block Protect Register 343 344 ;* Breakpoint Module (BRK) *********************** ************************* 345 0000 346 brkh equ $FE0C ; Break Address Register High 0000 347 brkl equ $FE0D ; Break Address Register Low 0000 348 brkscr equ $FE0E ; Break Status and Control Register 0000 349 BRKE equ 7 ; break enable bit 0000 350 BRKA equ 6 ; break active bit 351 352 ;* Low-Voltage Inhibit (LVI) ********************* ************************* 353 0000 354 lvisr equ $FE0F ; LVI Status Register 0000 355 LVIOUT equ 7 ; LVI output bit 356 357 ;* EEPROM programming registers ******************* *************************** 358 0000 359 EEDIVHNVR equ $FE10 360 0000 361 EEDIVLNVR equ $FE11 362 0000 363 EEDIVH equ $FE1A 364 0000 365 EEDIVL equ $FE1B 366 0000 367 eenvr equ $FE1C ;EEPROM Array Config Reg HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 11 0000 368 EEPRTCT equ 16 ;protection bit 0000 369 EEBP3 equ 8 ;block potection bit 3 0000 370 EEBP2 equ 4 ;block potection bit 2 0000 371 EEBP1 equ 2 ;block potection bit 1 0000 372 EEBP0 equ 1 ;block potection bit 0 373 0000 374 eecr equ $FE1D ;EEPROM Control Reg 0000 375 EEDUM equ 128 ;dummy bit 0000 376 EEOFF equ 32 ;power off 0000 377 EERAS1 equ 16 ;erase/program mode select bit 1 0000 378 EERAS0 equ 8 ;erase/program mode select bit 0 0000 379 EELAT equ 4 ;latch control 0000 380 EEAUTO equ 2 ;automatic termination of prgm/erase cycle 0000 381 EEPGM equ 1 ;program/erase enable 382 0000 383 EEACR equ $FE1F 384 385 ;* Computer Operating Properly (COP) ************* ************************* 386 0000 387 copctl equ $FFFF ; COP Control Register 388 389 ;*************************************************** ********* 390 ; VECTORS 391 ;*************************************************** ********* 392 0000 393 dbg_vectors equ $FAD0 ; Debug Vectors 394 0000 395 Vectors: equ $ffd0 396 0000 397 ivadc: equ $ffd0 ; Vector for A/D conversion Complete 0000 398 ivkey: equ $ffd2 ; Vector for Keyboard 0000 399 ivsctx: equ $ffd4 ; Vector for SCI Tx 0000 400 ivscrx: equ $ffd6 ; Vector for SCI Rx 0000 401 ivscer: equ $ffd8 ; Vector for SCI Error 0000 402 equ $ffda ; Reserved 0000 403 equ $ffdc ; Reserved 0000 404 ivtb3: equ $ffde ; TIMB Channel 3 Vector HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 12 0000 405 ivtb2: equ $ffe0 ; TIMB Channel 2 Vector 0000 406 ivsptx: equ $ffe2 ; Vector for SPI Tx 0000 407 ivsprx: equ $ffe4 ; Vector for SPI Rx 0000 408 ivtbof: equ $ffe6 ; TIMB Overflow Vector 0000 409 ivtb1: equ $ffe8 ; TIMB Channel 1 Vector 0000 410 ivtb0: equ $ffea ; TIMB Channel 0 Vector 0000 411 ivtao: equ $ffec ; TIMA Overflow Vector 0000 412 ivt1c1: equ $ffee ; TIMA Channel 3 Vector 0000 413 ivta2: equ $fff0 ; TIMA Channel 2 Vector 0000 414 ivta1: equ $fff2 ; TIMA Channel 1 Vector 0000 415 ivta0: equ $fff4 ; TIMA Channel 0 Vector 0000 416 ivtof: equ $fff6 ; TIM Overflow Vector 0000 417 ivpll: equ $fff8 ; PLL Vector 0000 418 ivirq: equ $fffa ; ~IRQ1 Vector 0000 419 ivswi: equ $fffc ; SWI Vector 0000 420 ivrst: equ $fffe ; Reset Vector 421 422 423 ;*************************************************** ********* 424 ;* Memory Map 425 ;*************************************************** ********* 426 0000 427 ram_start equ $0050 ; start of RAM 0000 428 zpage_end equ $00FF ; End of zero page ram 0000 429 extraram equ $0100 ; Start of Extra RAM 0000 430 usr_stack equ $01ff ; Bottom of user stack 0000 431 ram_last equ $023F ; last RAM location 0000 432 rom_start equ $8000 ; start of ROM 0000 433 rom_last equ $FAFF ; last ROM location ($FDFF??) 434 435 436 ;(C)opywrite P&E Microcomputer Systems, 2000 (www.pemicro.com) 437 ; You may use this code freely as long as this copyright notice 438 ; and website address is included and un-modified. 439 0000 440 include "../macros.inc" ; Macro instruction definition 441 ; -------------------------------------------------- ----------------- HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 13 442 ; Macro Definitions 443 ; -------------------------------------------------- ----------------- 444 0000 445 #macro aax macro 446 psha 447 pshx 448 add 1,sp 449 pulx 450 tax 451 bcc *+7 ; Branch to below 452 pshh 453 inc 1,sp 454 pulh 455 ; Branch to here 456 pula 0000 457 #macroend 458 0000 459 #macro inch macro 460 pshh 461 inc 1,sp 462 pulh 0000 463 #macroend 464 0000 465 #macro tha macro 466 pshh 467 pula 0000 468 #macroend 469 0000 470 #macro tah macro 471 psha 472 pulh 0000 473 #macroend 474 0000 475 #macro pshhx macro 476 pshx 477 pshh 0000 478 #macroend 479 0000 480 #macro pulhx macro 481 pulh 482 pulx 0000 483 #macroend 484 0000 485 #macro ldhxx macro 486 lda ,x 487 ldx 1,x 488 psha 489 pulh 0000 490 #macroend 491 0000 492 include "../local.inc" ; Local variables 493 ; 494 ; Conditional Assembly Directives *************** ************************* 495 ; 496 HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 14 0000 497 #setnot HYPERTERM ; enable slow Hyperterminal communications 498 499 ; 500 ; Microcontroller Peripheral Equates ************ ************************* 501 ; 502 0000 503 boot_start equ $E000 ; start of protected Bootloader 0000 504 flash_protect equ {(boot_start>7)&$FF} ; Flash Block Protect Reg value 0000 505 flash_page equ 128T ; Flash Erase Page size 506 0000 507 init_config1 equ %00000011 ; initial Configurat ion Register 1 508 ; Bit_7=0 - LVISTOP - LVI disabled during stop mode 509 ; Bit_6 unused 510 ; Bit_5=0 - LVIRSTD - LVI reset enabled during run mode 511 ; Bit_4=0 - LVIPWRD - Power enabled to LVI module 512 ; Bit_3=0 - SSREC - Stop recovery after 4096 cycles 513 ; Bit_2=0 - COPRS - COP rate (2**18 - 2**4) 514 ; Bit_1=1 - STOP - Stop Instruction disabled 515 ; Bit_0=1 - COPD - COP Disabled 516 ; 0000 517 RXBLEN equ 14T ; Serial I/O Receive buffer length 0000 518 STACK_ALLOC equ 32T ; Monitor Stack Allocation 519 ; 0000 520 init_scc1 equ %01000000 ; enable SCI, 8-bits, no par, 1 stop 0000 521 init_scc2 equ %00001100 ; no interupts, rcvr and tmtr enabled 0000 522 init_scbr equ %00000011 ; set SCI for 9600 baud 523 ; 524 ; ASCII character definitions 525 0000 526 SPACE equ $20 ; ASCII space 0000 527 CR equ $0D ; ASCII carriage return 0000 528 LF equ $0A ; ASCII linefeed 0000 529 NUL equ $00 ; ASCII linefeed 0000 530 BS equ $08 ; ASCII Backspace key 0000 531 XOFF equ $13 ; ASCII X-Off key (^S or DC3) 0000 532 XON equ $11 ; ASCII X-On key (^S or DC1) 0000 533 ESC equ $1B ; ASCII Escape Character 534 HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 15 535 ;--------------------------------------------------- ---- 536 ; TIMING FOR fbus = 0.407 us 537 ;the internal clock fBUS runs at 1/2.4576 ^6 = 0.407 uS. 538 ;The DBNZ instruction takes 3 cycles, which makes 1.22 uS 539 ;us5 EQU 5 ;5 * 1.22 = 6.1 uS 540 ;us10 EQU 9 ;9 * 1.22 = 10.9 uS 541 ;us30 EQU 25 ;25 * 1.22 = 30.5 uS 542 ;us100 EQU 82 ;82 * 1.22 = 100 543 ;ms1 EQU 10 ;10 * 82 * 1.22 = 1.00 mS 544 545 ;--------------------------------------------------- ----- 546 ; TIMING FOR fbus = 0.115 us 547 ;The DBNZ instruction takes 3 cycles, which makes 0.344 uS 0000 548 us1 EQU 3 ;3 * 0.344 = 1.032 uS 0000 549 us5 EQU 18 ;18 * 0.344 = 6.1 uS 0000 550 us10 EQU 32 ;32 * 0.344 = 10.9 uS 0000 551 us30 EQU 89 ;89 * 0.344 = 30.5 uS 0000 552 us50 EQU 148 ;148 * 0.344 = 51 us 0000 553 ms1 EQU 36 ;36 * 82 * 0.344 = 1.00 mS 554 0000 555 tpgs EQU us5 ;times taken from MC68HC908AB32/D rev 1 0000 556 tnvs EQU us10 0000 557 tprog EQU us30 0000 558 tnvh EQU us5 0000 559 terase EQU ms1 560 561 ; User Base RAM 562 0050 563 org $50 0050 564 _count rmb 1 ; Byte Counter for s record download 0051 565 _temp_sp rmb 2 ; Temporary stack pointer 566 567 ; User stack - Hex 3ff 568 03FF 569 org $3FF 03FF 570 _user_stack rmb 1 ; Position to Initialize user stack 571 572 ; Monitor RAM - Hex 400-44F 573 0400 574 org $400 0400 575 _hbufpos rmb 2 ; buffer position temp storage 0402 576 _tempx rmb 2 ; Temporary HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 16 h:x register storage 0404 577 _stack_save rmb 2 ; Stack save 0406 578 _last_break rmb 2 ; Save last break, to reset break 579 ; when resuming 0408 580 _h_save rmb 1 ; h-reg save 0409 581 _state rmb 1 ; State after break point 040A 582 _inbuf rmb RXBLEN ; Input Buffer 583 584 ; Monitor stack, initialize at end of RAM Hex 23F 585 044F 586 org $44F 044F 587 _mon_stack rmb 1 ; Position of monitor stack 588 803C 589 org $803C 803C [04] 81 590 rts ; routine location for Monitor hook into User App 591 EF00 592 org $EF00 EF00 8040 593 _user_reset fdb $8040 ; pointer to start User Application 594 595 ;*************************************************** ********* 596 ; Power-on Reset 597 ;*************************************************** ********* 598 __start: 599 _bootreset: 600 ; Launch the bootloader from power-on reset. 601 EF02 [02] 9B 602 sei ; disable all interupts EF03 [03] 450450 603 ldhx #_mon_stack+1 ; initialize EF06 [02] 94 604 txs ; the stack pointer 605 606 ; Initialize the PLL CGM for 7.372800 MHz bus speed from 32.768 kHz crystal. 607 EF07 [05] CDF200 608 jsr PLLset ; change bus speed 609 610 ; Initialize the SCI. 611 EF0A [04] 6E0319 612 mov #init_scbr,scbr ; initialize baud rate EF0D [04] 6E4013 613 mov #init_scc1,scc1 ; initialize SCI Control Register 1 EF10 [04] 6E0C14 614 mov #init_scc2,scc2 ; initialize SCI Control Register 2 EF13 [04] 6E031F 615 mov #init_config1,config1 ; init HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 17 Configuration Register 1 616 617 ; Test Port F7 for "Monitor Jumper" 618 ; Entry to Monitor = jumper OFF ==> F7 = 1 619 ; Entry to User Pgm = jumper ON ==> F7 = 0 620 EF16 [04] 6E400D 621 mov #$40,ddrf ;set portf bits 7,5,4,3,2,1,0 as inputs, bit 6 (LED) as output EF19 [04] 6EB83E 622 mov #$B8,prtfpu ;assign pullups to Port F bits 7,5,4,3 EF1C [04] 1D09 623 bclr 6,portf ;turn LED on continuously while in monitor EF1E [05] 0F0909 624 brclr 7,portf,MonStart ;go start Monitor if "Monitor Jumper" is in place EF21 [03] 4503FF 625 ldhx #_user_stack ;else init user SP EF24 [05] CDF149 626 jsr _save_sp ; in _user_stack area EF27 [05] CD8040 627 jsr $8040 ; and go start User application at $8040 628 629 MonStart: EF2A [03] 450050 630 ldhx #ram_start EF2D [02] 7F 631 clrRAM: clr ,x ;Clear RAM EF2E [02] AF01 632 aix #1 EF30 [03] 650240 633 cphx #ram_last+1 EF33 [03] 26F8 634 bne clrRAM 635 EF35 [05] CDEF6E 636 jsr _init_ustack ;Initialize user stack 637 EF38 [05] CD803C 638 jsr $803C ;display message to LCD via Monitor hook in User App 639 640 ; Boot start 641 _boot: EF3B [04] C7FFFF 642 sta copctl ;clear the COP counter EF3E [02] A6FF 643 lda #$FF EF40 [05] CDF299 644 jsr _delay ;delay just a bit EF43 [03] 45F3A3 645 ldhx #_PWR_MSG ;point to monitor sign-on message EF46 [05] CDF60A 646 jsr _puts ;and display it 647 _main: EF49 [03] 45F308 648 ldhx #_PROMPT ; Print prompt EF4C [05] CDF60A 649 jsr _puts EF4F [05] CDF4EE 650 jsr _gets ;get user input command string EF52 [03] 25F5 651 bcs _main ;keep looking if ESC or ctl-C EF54 [04] C6040A 652 lda _inbuf ;check input buffer HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 18 EF57 [03] 27F0 653 beq _main ;keep looking if empty (just CR entered) EF59 [02] A4DF 654 and #$DF ;turn to capital letter EF5B [03] 45F2E0 655 ldhx #_cmdtab ;point to command table EF5E [05] CDF62E 656 jsr _get_atbl ;get menu selection EF61 [03] 2403 657 bcc notfound ;valid menu item not selected EF63 [04] FD 658 jsr ,x ;found menu item, call corresponding routine EF64 [03] 20E3 659 bra _main ;get another command when processing done 660 notfound: EF66 [03] 45F3D8 661 ldhx #_ERR_MSG ;pointer to error string EF69 [05] CDF60A 662 jsr _puts ;print the string EF6C [03] 20DB 663 bra _main ;go get another command 664 665 ;*************************************************** ********* 666 ; _init_ustack After power up or download, checks for 667 ; valid user reset jump statement. If one exists, 668 ; then initialize user stack to go there on an rti 669 ;*************************************************** ********* 670 _init_ustack: EF6E [05] 0F0912 671 brclr 7,PortF,no_rst_vec ; "Mon Jumper" in place, we're in Monitor EF71 [03] 4503FB 672 ldhx #_user_stack-4 ; Read user stack address + rti frame EF74 [05] CDF149 673 jsr _save_sp ; Store address in stack_save EF77 [04] C6EF00 674 lda _user_reset ; Get address of user program reset EF7A [04] C703FE 675 sta _user_stack-1 ; and store in address field of stack frame EF7D [04] C6EF01 676 lda _user_reset+1 ; EF80 [04] C703FF 677 sta _user_stack 678 no_rst_vec: EF83 [04] 81 679 rts 680 681 ;*************************************************** ********* 682 ; _medit() Edit memory locations 683 ;*************************************************** ********* 684 _medit: EF84 [05] CDF677 685 jsr _first_hex EF87 [03] 252F 686 bcs end_medit 687 mexlp: EF89 [05] CDF586 688 jsr _crlf HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 19 EF8C [05] CDF5AD 689 jsr _pword EF8F [02] F6 690 lda ,x EF90 [05] CDF5B9 691 jsr _pbyte_sp EF93 [05] CDF592 692 jsr _space EF96 [02] A602 693 lda #2 EF98 macro 694 pshhx EF98 [02] 89 695 PSHX EF99 [02] 8B 696 PSHH EF9A [05] CDF67E 697 jsr _gethex EF9D [04] C6040A 698 lda _inbuf EFA0 [03] 2508 699 bcs not_byte EFA2 [01] 9F 700 txa EFA3 [02] 8A 701 pulh EFA4 [02] 88 702 pulx EFA5 [02] F7 703 sta ,x EFA6 [02] AF01 704 aix #1 EFA8 [03] 20DF 705 bra mexlp 706 not_byte: EFAA macro 707 pulhx EFAA [02] 8A 708 PULH EFAB [02] 88 709 PULX EFAC [02] AF01 710 aix #1 EFAE [02] A120 711 cmp #SPACE EFB0 [03] 27D7 712 beq mexlp ; If nul entry (ENTER), go to next byte EFB2 [02] AFFE 713 aix #-2 EFB4 [02] A108 714 cmp #BS EFB6 [03] 27D1 715 beq mexlp ; If Backspace, go to previous byte 716 end_medit: EFB8 [04] 81 717 rts ; Else return 718 719 ;*************************************************** ********* 720 ; _dump() Dump Memory locations 721 ;*************************************************** ********* 722 _dump: EFB9 [05] CDF677 723 jsr _first_hex EFBC [03] 252E 724 bcs end_dump EFBE [01] 9F 725 txa ; Init even boundary EFBF [02] A4F0 726 and #$F0 EFC1 [01] 97 727 tax 728 prmem: EFC2 macro 729 pshhx EFC2 [02] 89 730 PSHX EFC3 [02] 8B 731 PSHH EFC4 [03] 45F312 732 ldhx #_HEADING EFC7 [05] CDF60A 733 jsr _puts EFCA macro 734 pulhx EFCA [02] 8A 735 PULH EFCB [02] 88 736 PULX 737 prmlp: EFCC [01] 9F 738 txa EFCD [02] A40F 739 and #$0F EFCF [03] 260C 740 bne nxmem EFD1 [05] CDF586 741 jsr _crlf EFD4 macro 742 tha HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 20 EFD4 [02] 8B 743 PSHH EFD5 [02] 86 744 PULA EFD6 [05] CDF5BE 745 jsr _pbyte EFD9 [01] 9F 746 txa EFDA [05] CDF58F 747 jsr _byte_sp 748 nxmem: EFDD [02] F6 749 lda ,x EFDE [05] CDF58F 750 jsr _byte_sp EFE1 [02] AF01 751 aix #1 EFE3 [01] 9F 752 txa EFE4 [01] 4D 753 tsta EFE5 [03] 26E5 754 bne prmlp 755 wt_end_dump: EFE7 [05] CDF5F6 756 jsr _do_again EFEA [03] 27D6 757 beq prmem 758 end_dump: EFEC [04] 81 759 rts 760 761 ;*************************************************** ********* 762 ;*************************************************** ********* 763 ; 764 ; D E B U G C O M M A N D S 765 ; 766 ;*************************************************** ********* 767 ;*************************************************** ********* 768 769 ;*************************************************** ********* 770 ; _fill() -- Fill Memory locations 771 ;*************************************************** ********* 772 _fill: EFED [05] CDF677 773 jsr _first_hex EFF0 [03] 252E 774 bcs end_fill EFF2 macro 775 pshhx EFF2 [02] 89 776 PSHX EFF3 [02] 8B 777 PSHH EFF4 [05] CDF66C 778 jsr _next_hex EFF7 [03] 2404 779 bcc get_val EFF9 macro 780 pulhx EFF9 [02] 8A 781 PULH EFFA [02] 88 782 PULX EFFB [03] 2023 783 bra end_fill 784 get_val: EFFD macro 785 tha EFFD [02] 8B 786 PSHH EFFE [02] 86 787 PULA EFFF [04] C70402 788 sta _tempx F002 [04] CF0403 789 stx _tempx+1 F005 [05] CDF66C 790 jsr _next_hex F008 [01] 9F 791 txa F009 macro 792 pulhx F009 [02] 8A 793 PULH F00A [02] 88 794 PULX HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 21 F00B [03] 2513 795 bcs end_fill 796 fill_lp: F00D [02] F7 797 sta ,x F00E [02] 87 798 psha F00F macro 799 tha F00F [02] 8B 800 PSHH F010 [02] 86 801 PULA F011 [04] C10402 802 cmp _tempx F014 [02] 86 803 pula F015 [03] 2605 804 bne nxt_fill F017 [04] C30403 805 cpx _tempx+1 F01A [03] 2704 806 beq end_fill 807 nxt_fill: F01C [02] AF01 808 aix #1 F01E [03] 20ED 809 bra fill_lp 810 end_fill: F020 [04] 81 811 rts 812 813 ;*************************************************** ********* 814 ; _pr_reg, _out_reg -- Outputs registers from user stack 815 ;*************************************************** ********* 816 _prreg: F021 [05] CDF586 817 jsr _crlf 818 _out_reg: F024 [03] 45F4BB 819 ldhx #SP_MSG F027 [05] CDF60A 820 jsr _puts F02A [05] CDF140 821 jsr _get_sp F02D [02] AFFF 822 aix #-1 F02F [05] CDF5AD 823 jsr _pword F032 macro 824 pshhx F032 [02] 89 825 PSHX F033 [02] 8B 826 PSHH F034 [03] 45F4BF 827 ldhx #CC_MSG 828 reg_lp: F037 [05] CDF60A 829 jsr _puts F03A [02] AF01 830 aix #1 F03C macro 831 pshhx F03C [02] 89 832 PSHX F03D [02] 8B 833 PSHH F03E [02] F6 834 lda ,x F03F [02] A13A 835 cmp #':' F041 [03] 2608 836 bne not_h_reg F043 [04] C60408 837 lda _h_save F046 [05] CDF5BE 838 jsr _pbyte F049 [03] 2016 839 bra nxt_reg 840 not_h_reg: F04B [04] 9EE603 841 lda 3,sp F04E macro 842 tah F04E [02] 87 843 PSHA F04F [02] 8A 844 PULH F050 [04] 9EEE04 845 ldx 4,sp F053 [02] AF01 846 aix #1 F055 [02] F6 847 lda ,x F056 [05] CDF5BE 848 jsr _pbyte F059 macro 849 tha HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 22 F059 [02] 8B 850 PSHH F05A [02] 86 851 PULA F05B [04] 9EE703 852 sta 3,sp F05E [04] 9EEF04 853 stx 4,sp 854 nxt_reg: F061 macro 855 pulhx F061 [02] 8A 856 PULH F062 [02] 88 857 PULX F063 [02] F6 858 lda ,x F064 [02] A145 859 cmp #'E' F066 [03] 26CF 860 bne reg_lp F068 macro 861 pulhx F068 [02] 8A 862 PULH F069 [02] 88 863 PULX F06A [04] 81 864 rts 865 866 ;*************************************************** ********* 867 ; _set_break -- Sets breakpoint 868 ;*************************************************** ********* 869 _set_break: F06B [05] CDF677 870 jsr _first_hex ; Gets breakpoint address F06E [03] 250A 871 bcs pr_brkpt F070 macro 872 tha ; store breakpoint so that it can be restored F070 [02] 8B 873 PSHH F071 [02] 86 874 PULA F072 [04] C70406 875 sta _last_break ; at next breakpoint when resuming F075 [04] CF0407 876 stx _last_break+1 F078 [04] AD1F 877 bsr _wt_break 878 pr_brkpt: F07A [03] 45F399 879 ldhx #_MSG_BREAK F07D [05] CDF60A 880 jsr _puts F080 [04] C6FE0E 881 lda brkscr F083 [03] 2A0B 882 bpl end_set_bp F085 [04] C6FE0C 883 lda brkh F088 macro 884 tah F088 [02] 87 885 PSHA F089 [02] 8A 886 PULH F08A [04] CEFE0D 887 ldx brkl F08D [05] CDF5AD 888 jsr _pword 889 end_set_bp: F090 [04] 81 890 rts 891 892 ;*************************************************** ********* 893 ; _restore_bk -- Restores break address to last set value 894 ;*************************************************** ********* 895 _restore_break: F091 [04] C60406 896 lda _last_break F094 macro 897 tah F094 [02] 87 898 PSHA F095 [02] 8A 899 PULH HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 23 F096 [04] CE0407 900 ldx _last_break+1 901 902 ; _wt_break writes a break point at h:x 903 904 _wt_break: F099 [04] CFFE0D 905 stx brkl ; stores breakpoint F09C macro 906 tha F09C [02] 8B 907 PSHH F09D [02] 86 908 PULA F09E [04] C7FE0C 909 sta brkh F0A1 [02] A680 910 lda #$80 F0A3 [04] C7FE0E 911 sta brkscr ; enables breakpoint F0A6 [04] C7FE03 912 sta sbfcr ; Allows access to break status registers F0A9 [04] 81 913 rts 914 915 ;*************************************************** ********* 916 ; _clr_break -- Clears breakpoint 917 ;*************************************************** ********* 918 _clr_break: F0AA [01] 4F 919 clra ; disables breakpoint F0AB [04] C7FE0E 920 sta brkscr F0AE [04] 81 921 rts 922 923 ;*************************************************** ********* 924 ; _break_pt -- Routine to process breakpoint 925 ;*************************************************** ********* 926 _break_pt: F0AF [02] 9B 927 sei F0B0 [02] A680 928 lda #$80 F0B2 [04] C7FE03 929 sta sbfcr ; Allows access to break status registers F0B5 [04] C7FE0E 930 sta brkscr F0B8 macro 931 tha F0B8 [02] 8B 932 PSHH F0B9 [02] 86 933 PULA F0BA [04] C70408 934 sta _h_save ; Save h register F0BD [02] 95 935 tsx F0BE [05] CDF149 936 jsr _save_sp ; Save user stack pointer F0C1 [03] 450450 937 ldhx #_mon_stack+1 ; Transfer stack to monitor RAM F0C4 [02] 94 938 txs F0C5 [04] ADCA 939 bsr _restore_break ; restore breakpoint F0C7 [04] C60409 940 lda _state ; Check if this was a go from a breakpoint F0CA [02] A101 941 cmp #1 ; If so, we need to resume F0CC [03] 2607 942 bne not_resume F0CE [01] 4F 943 clra ; Clear resume state F0CF [04] C70409 944 sta _state F0D2 [03] CCF18F 945 jmp _do_rti ; Resume from current breakpoint 946 not_resume: HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 24 F0D5 [03] 45F399 947 ldhx #_MSG_BREAK ; Output breakpoint message F0D8 [05] CDF60A 948 jsr _puts F0DB [05] CDF024 949 jsr _out_reg ; Output registers F0DE [05] CDF12F 950 jsr _get_pc ; Get current user program counter F0E1 [05] CDF715 951 jsr _disasm_1x ; Disassemble where you are F0E4 [04] C60409 952 lda _state F0E7 [02] A102 953 cmp #2 ; Is it in single step mode? F0E9 [03] 2609 954 bne not_sstep ; If not, go back to prompt F0EB [05] CDF5F6 955 jsr _do_again ; If so, look for space to step next F0EE [03] 270B 956 beq _step_again ; If space, do next instruction F0F0 [01] 4F 957 clra ; If not, clear resume state F0F1 [04] C70409 958 sta _state ; and go back to prompt 959 not_sstep: F0F4 [03] CCEF49 960 jmp _main 961 962 ;*************************************************** ********* 963 ; _next -- Step one instruction 964 ;*************************************************** ********* 965 _next: F0F7 [04] AD22 966 bsr _is_stack_ok ; Only step if Stack is initialized F0F9 [03] 2533 967 bcs no_step ; WARNING: this is not a bullet-proof test! 968 _step_again: F0FB [04] AD08 969 bsr _break_next ; Set breakpoint to stop at next instruction F0FD [02] A602 970 lda #2 ; Sets single step state F0FF [04] C70409 971 sta _state F102 [03] CCF16B 972 jmp _go_stack ; 973 974 ;*************************************************** ********* 975 ; _break_next -- Set to break on next instruction Based on following: 976 ; - If current instruction is 2 or more bytes 977 ; setting the break in the 2nd byte will cause 978 ; the break to occur on the next instruction 979 ; - If one byte instruction, only jsr ,x and 980 ; jmp ,x will start at next byte 981 ;*************************************************** ********* 982 _break_next: F105 [05] CDF12F 983 jsr _get_pc ; Get current user program HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 25 counter F108 [02] F6 984 lda ,x F109 [02] AF01 985 aix #1 ; Check if instruction is a jmp ,x or jsr ,x F10B [02] A4FE 986 and #$FE F10D [02] A1FC 987 cmp #$FC F10F [03] 2607 988 bne not_jx F111 [04] AD24 989 bsr _get_hx F113 [02] F6 990 lda ,x ; If it is a jmp ,x or jsr ,x F114 [03] EE01 991 ldx 1,x ; Then set break at address pointed to by x-reg F116 macro 992 tah F116 [02] 87 993 PSHA F117 [02] 8A 994 PULH 995 not_jx: F118 [03] CCF099 996 jmp _wt_break 997 998 ;*************************************************** ********* 999 ; _is_stack_ok returns carry clear if ok, set if not, 1000 ; 1001 ;*************************************************** ********* 1002 _is_stack_ok: F11B [04] C60404 1003 lda _stack_save ; Check that user SP is valid F11E [03] 2706 1004 beq ck_ss_low F120 [02] A101 1005 cmp #1 F122 [03] 2609 1006 bne stk_not_ok F124 [03] 2005 1007 bra stk_ok 1008 ck_ss_low: F126 [04] C60405 1009 lda _stack_save+1 F129 [03] 2702 1010 beq stk_not_ok 1011 stk_ok: F12B [01] 98 1012 clc F12C [04] 81 1013 rts 1014 stk_not_ok: F12D [01] 99 1015 sec 1016 no_step: 1017 end_go: F12E [04] 81 1018 rts 1019 1020 ;*************************************************** ********* 1021 ; _get_pc Gets user PC off of user stack, returned in h:x reg 1022 ;*************************************************** ********* 1023 _get_pc: F12F [04] AD0F 1024 bsr _get_sp F131 [03] E603 1025 lda 3,x F133 [03] EE04 1026 ldx 4,x F135 [03] 200F 1027 bra done_get 1028 1029 ;*************************************************** ********* HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 26 1030 ; _get_hx Gets user h:x reg, gets x-reg off of stack and 1031 ; h reg from _h_save. Returns in h:x reg 1032 ;*************************************************** ********* 1033 _get_hx: F137 [04] AD07 1034 bsr _get_sp F139 [03] EE02 1035 ldx 2,x F13B [04] C60408 1036 lda _h_save F13E [03] 2006 1037 bra done_get 1038 1039 ;*************************************************** ********* 1040 ; _get_sp Gets user stack pointer from +stack_save 1041 ; Returns in h:x reg 1042 ;*************************************************** ********* 1043 _get_sp: F140 [04] C60404 1044 lda _stack_save F143 [04] CE0405 1045 ldx _stack_save+1 1046 done_get: F146 macro 1047 tah F146 [02] 87 1048 PSHA F147 [02] 8A 1049 PULH F148 [04] 81 1050 rts 1051 1052 ;*************************************************** ********* 1053 ; _save_sp Saves user stack pointer in stack_save 1054 ; Passed in h:x reg 1055 ;*************************************************** ********* 1056 _save_sp: F149 macro 1057 tha F149 [02] 8B 1058 PSHH F14A [02] 86 1059 PULA F14B [04] C70404 1060 sta _stack_save ; Store address in stack_save F14E [04] CF0405 1061 stx _stack_save+1 F151 [04] 81 1062 rts 1063 1064 ;*************************************************** ********* 1065 ; go(*x-reg) Execute program at X-reg 1066 ;*************************************************** ********* 1067 _go: F152 [05] CDF677 1068 jsr _first_hex F155 [03] 2510 1069 bcs chk_stack_add F157 macro 1070 tha F157 [02] 8B 1071 PSHH F158 [02] 86 1072 PULA F159 [04] CF0402 1073 stx _tempx F15C [03] 450400 1074 ldhx #_user_stack+1 F15F [02] 94 1075 txs HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 27 F160 macro 1076 tah F160 [02] 87 1077 PSHA F161 [02] 8A 1078 PULH F162 [04] CE0402 1079 ldx _tempx F165 [02] 9A 1080 cli F166 [02] FC 1081 jmp ,x ; Call user prog,x 1082 chk_stack_add: F167 [04] ADB2 1083 bsr _is_stack_ok F169 [03] 25C3 1084 bcs end_go 1085 _go_stack: F16B [04] C6FE0E 1086 lda brkscr F16E [03] 2A1F 1087 bpl _do_rti F170 [05] CDF12F 1088 jsr _get_pc ; Get current user program counter F173 [04] C3FE0D 1089 cpx brkl ; compares breakpoint address to current F176 [03] 2617 1090 bne _do_rti F178 macro 1091 tha F178 [02] 8B 1092 PSHH F179 [02] 86 1093 PULA F17A [04] C1FE0C 1094 cmp brkh F17D [03] 2610 1095 bne _do_rti F17F [02] A601 1096 lda #1 ; If currently at breakpoint, set _state to 1 F181 [04] C70409 1097 sta _state ; to indicate to continue from next break F184 macro 1098 tha ; and store breakpoin t to be restored F184 [02] 8B 1099 PSHH F185 [02] 86 1100 PULA F186 [04] C70406 1101 sta _last_break ; at next breakpoint when resuming F189 [04] CF0407 1102 stx _last_break+1 F18C [05] CDF105 1103 jsr _break_next ; and set break at next instruction 1104 _do_rti: F18F [04] ADAF 1105 bsr _get_sp ; If user SP is valid, set SP to user SP and do RTI F191 [02] 94 1106 txs F192 [04] C60408 1107 lda _h_save F195 macro 1108 tah F195 [02] 87 1109 PSHA F196 [02] 8A 1110 PULH F197 [07] 80 1111 rti 1112 1113 ;*************************************************** ********* 1114 ; Prints Help message 1115 ;*************************************************** ********* 1116 _help: F198 [03] 45F3A3 1117 ldhx #_PWR_MSG F19B [05] CDF60A 1118 jsr _puts F19E [03] 45F3DD 1119 ldhx #_HELPLIST F1A1 [05] CDF60A 1120 jsr _puts F1A4 [04] 81 1121 rts 1122 1123 ;*************************************************** HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 28 ********* 1124 ; Copy Flash Mass Erase algorithm into RAM and execute. 1125 ;*************************************************** ********* 1126 1127 ; ram_exec equ $200-STACK_ALLOC-ProgramRamSiz e+1 ; executable RAM 1128 F1A5 1129 ram_exec equ $19A 1130 1131 _do_mass_erase: F1A5 [03] 45003B 1132 ldhx #EraseRamSize ; initialize pointer 1133 BootErase1: F1A8 [04] D6F268 1134 lda MassErase-1,x ; get program from Flash F1AB [04] D70199 1135 sta ram_exec-1,x ; copy into RAM F1AE [03] 5BF8 1136 dbnzx BootErase1 ; decrement pointer and loop back until done F1B0 [05] CD019A 1137 jsr ram_exec ; execute Flash Mass Erase algorithm from RAM 1138 BootDone: F1B3 [05] CDEF6E 1139 jsr _init_ustack ; initialize user stack F1B6 [04] 81 1140 rts 1141 1142 ;--------------------------------------------------- ---------------- 1143 ; Check for Program Flash command. 1144 1145 _do_dnload: 1146 ; Copy Program Flash algorithm into RAM and execute. 1147 F1B7 [03] 450047 1148 ldhx #ProgramRamSize ; initialize pointer 1149 BootProg: F1BA [04] D6F298 1150 lda _delay-1,x ; get program from Flash F1BD [04] D70199 1151 sta ram_exec-1,x ; copy into RAM F1C0 [03] 5BF8 1152 dbnzx BootProg ; decrement pointer and loop back until done F1C2 [03] 45F380 1153 ldhx #_MSG_WAITING ; point to waiting message F1C5 [05] CDF60A 1154 jsr _puts ; output it 1155 1156 ; Get S-Record from host. 1157 BootProg1: F1C8 [04] C7FFFF 1158 sta copctl ; clear the COP counter F1CB [02] 95 1159 tsx ; get the Stack Pointer F1CC [04] 3551 1160 sthx _temp_sp ; save it temporarily F1CE [02] A7DC 1161 ais #-36T ; allocate stack space for data F1D0 [05] CDF211 1162 jsr GetSRec ; get an S-Record F1D3 [03] 2620 1163 bne BootProg3 ; indicate error if S-Record is invalid F1D5 [02] 86 1164 pula ; get S-Record type HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 29 F1D6 [02] A139 1165 cmp #'9' ; check for end record type F1D8 [03] 270B 1166 beq BootProg2 ; indicate operation complete F1DA [02] A131 1167 cmp #'1' ; check for data record type F1DC [03] 2617 1168 bne BootProg3 ; indicate error if S-Record is invalid 1169 1170 ; Program Flash. 1171 F1DE [05] CD01A5 1172 jsr {ram_exec+ProgramRam} ; execute Program Flash alg from RAM F1E1 [02] A723 1173 ais #35T ; deallocate stack space F1E3 [03] 20E3 1174 bra BootProg1 ; loop bacl for next S-Record 1175 1176 BootProg2: F1E5 [02] A723 1177 ais #35T ; deallocate stack space F1E7 [05] 0B16C9 1178 brclr SCRF,scs1,BootDone ; skip if SCI receiver is empty F1EA [05] CDF5D7 1179 jsr _getchne ; else, clear last ASCII carriage 1180 ; return from the SCI F1ED [05] 0B16C3 1181 brclr SCRF,scs1,BootDone ; skip if SCI receiver is empty F1F0 [05] CDF5D7 1182 jsr _getchne ; else, clear last LF from the SCI F1F3 [03] 20BE 1183 bra BootDone ; indicate operation complete 1184 1185 BootProg3: F1F5 [02] A724 1186 ais #36T ; deallocate stack space 1187 1188 ; Respond to error situations. 1189 F1F7 [03] 45F38F 1190 ldhx #_MSG_ERROR ; point to error message 1191 Boot4: F1FA [05] CDF60A 1192 jsr _puts ; output it F1FD [03] CCEF3B 1193 jmp _boot ; jump back to the top 1194 1195 ;*************************************************** ***************** 1196 ; CGM PLL Bus Frequency Change Subroutine 1197 ; 1198 ; This subroutine will program the CGM PLL to change the bus frequency in accordance with 1199 ; the data being pointed to by H:X. 1200 ;*************************************************** ***************** 1201 PLLset: F200 [04] 191C 1202 bclr BCS,pctl ; select HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 30 external reference as base clock F202 [04] 1B1C 1203 bclr PLLON,pctl ; turn off PLL F204 [04] 6E771E 1204 mov #$77,PPG ; set up PLL Programming Register F207 [04] 1E1D 1205 bset AUTO,pbwc ; enable automatic bandwidth control F209 [04] 1A1C 1206 bset PLLON,pctl ; turn on PLL 1207 PLLwait: F20B [05] 0D1DFD 1208 brclr LOCK,pbwc,PLLwait ; wait for PLL to lock F20E [04] 181C 1209 bset BCS,pctl ; select VCO as base clock F210 [04] 81 1210 rts ; return 1211 1212 1213 ;*************************************************** ***************** 1214 ; GetSRec Subroutine 1215 ; 1216 ; This subroutine will retrieve data in S19 record format via the SCI. 1217 ; 1218 ; Calling convention: 1219 ; 1220 ; ais #-buffer_length 1221 ; jsr GetSRec 1222 ; 1223 ; Returns: CCRZ= 1 if valid S-Record retrieved. Otherwise, CCRZ= 0. 1224 ; S-Record Type at SP+1 (1 byte) 1225 ; S-Record Size at SP+2 (1 byte) 1226 ; S-Record Address at SP+3 (2 bytes) 1227 ; S-Record Data at SP+5 (up to 32 bytes, typically) 1228 ; 1229 ; | | <-sp (after local space allocation) 1230 ; H:X-> | SRecCount | 1231 ; | SRecChkSum | <-sp (when called) 1232 ; | ReturnAddr msb | 1233 ; | ReturnAddr lsb | <-sp (upon return) 1234 ; | SRecType | 1235 ; | SRecSize | 1236 ; H:X-> | SRecAddr msb | 1237 ; | SRecAddr lsb | 1238 ; | SRecData 00 | 1239 ; | SRecData 01 | etc.. 1240 ; 1241 ; Changes: ACC, H:X 1242 ;*************************************************** ***************** F211 1243 SRecCount equ 1 ; stack pointer offset for S-Record Counter (local) F211 1244 SRecChkSum equ 2 ; stack pointer offset for S-Record Check Sum (local) F211 1245 SRecType equ 5 ; stack pointer offset for HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 31 S-Record Type F211 1246 SRecSize equ 6 ; stack pointer offset for S-Record Size F211 1247 SRecAddr equ 7 ; stack pointer offset for S-Record Address F211 1248 SRedData equ 8 ; stack pointer offset for S-Record Data 1249 1250 GetSRec: F211 [02] A7FE 1251 ais #-2 ; allocate local variable space F213 [04] 9E6F06 1252 clr SRecSize,sp ; initialize S-Record size 1253 GetSRec1: F216 [05] CDF5D7 1254 jsr _getchne ; get a character from the SCI F219 1255 #if HYPERTERM F219 1256 #elseif F219 [05] CDF59C 1257 jsr _putch ; echo it back F21C 1258 #endif F21C [02] A10D 1259 cmp #CR ; check for ASCII carriage return F21E [03] 2605 1260 bne GetSRec1a ; just loop back if so F220 [02] A60A 1261 lda #LF ; get ASCII line feed F222 1262 #if HYPERTERM F222 1263 #elseif F222 [05] CDF59C 1264 jsr _putch ; echo it back F225 1265 #endif 1266 GetSRec1a: F225 [02] A153 1267 cmp #'S' ; check for start of record character F227 [03] 26ED 1268 bne GetSRec1 ; loop back if not F229 [05] CDF5D7 1269 jsr _getchne ; else, get next character from the SCI F22C 1270 #if HYPERTERM F22C 1271 #elseif F22C [05] CDF59C 1272 jsr _putch ; echo it back F22F 1273 #endif F22F [02] A130 1274 cmp #'0' ; check for header record type F231 [03] 27E3 1275 beq GetSRec1 ; loop back if so F233 [02] A139 1276 cmp #'9' ; else, check for end record type F235 [03] 2704 1277 beq GetSRec2 ; continue if so F237 [02] A131 1278 cmp #'1' ; else, check for data record type F239 [03] 26DB 1279 bne GetSRec1 ; loop back if not 1280 GetSRec2: F23B [04] 9EE705 1281 sta SRecType,sp ; save S-Record type F23E [05] CDF60E 1282 jsr GetHexByte ; get the S-Record length F241 [03] 2623 1283 bne GetSRec4 ; exit if not a valid hex byte F243 [04] 9EE701 1284 sta SRecCount,sp ; initialize S-Record counter F246 [04] 9EE702 1285 sta SRecChkSum,sp ; initialize S-Record check sum F249 [02] A003 1286 sub #3 ; adjust for address HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 32 and checksum F24B [04] 9EE706 1287 sta SRecSize,sp ; save S-Record size F24E [02] 95 1288 tsx ; use H:X as data stack frame pointer F24F [02] AF06 1289 aix #(SRecAddr-1) ; adjust so pointer starts at S-Record Address 1290 GetSRec3: F251 [05] CDF60E 1291 jsr GetHexByte ; get next S-Record hex byte F254 [03] 2610 1292 bne GetSRec4 ; exit if not a valid hex byte F256 [02] F7 1293 sta ,x ; save data in stack frame F257 [04] 9EEB02 1294 add SRecChkSum,sp ; add data to check sum F25A [04] 9EE702 1295 sta SRecChkSum,sp ; save new check sum F25D [02] AF01 1296 aix #1 ; move data stack frame pointer F25F [06] 9E6B01EE 1297 dbnz SRecCount,sp,GetSRec3 ; loop back until all data received F263 [05] 9E6C02 1298 inc SRecChkSum,sp ; final calc zeros check sum if it's okay 1299 GetSRec4: F266 [02] A702 1300 ais #2 ; deallocate local variables F268 [04] 81 1301 rts ; return 1302 1303 ;*************************************************** *********************** 1304 ; Flash Mass Erase Subroutine 1305 ; This subroutine performs multiple Page Erase operations in order 1306 ; to completely erase the application space Flash memory. 1307 ; This subroutine is copied into and executed from RAM. 1308 ;*************************************************** ***************** 1309 MassErase: F269 [03] 458000 1310 ldhx #rom_start ; initialize pointer to start of Flash memory 1311 1312 MassErase1: 1313 ; Set ERASE, read the Flash Block Protect Register and write any 1314 ; data into Flash page. F26C [02] A602 1315 lda #ERASE ; set ERASE control bit F26E [04] C7FE08 1316 sta flcr ; in Flash Control Register F271 [04] C6FF7E 1317 lda flbpr ; read from Flash Block Protect Register F274 [02] F7 1318 sta ,x ; write any data to address within page 1319 1320 ; Wait for >10us, then set HVEN. F275 [02] A601 1321 lda #1 ; wait F277 [04] AD20 1322 bsr _delay ; for 11.7us HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 33 F279 [02] A60A 1323 lda #(ERASE|HVEN) ; set HVEN control bit F27B [04] C7FE08 1324 sta flcr ; in Flash Control Register 1325 1326 ; Wait for >1ms, then clear ERASE. F27E [02] A664 1327 lda #100T ; wait F280 [04] AD17 1328 bsr _delay ; for 1.005ms F282 [02] A608 1329 lda #HVEN ; clear ERASE control bit F284 [04] C7FE08 1330 sta flcr ; in Flash Control Register 1331 1332 TestLabel: 1333 ; Wait for >5us, then clear HVEN. F287 [02] A601 1334 lda #1 ; wait F289 [04] AD0E 1335 bsr _delay ; for 11.7us F28B [01] 4F 1336 clra ; clear HVEN control bit F28C [04] C7FE08 1337 sta flcr ; in Flash Control Register 1338 1339 ; Advance pointer and repeat until finished. F28F [02] AF40 1340 aix #{flash_page/2} ; add half of Flash Erase Page size twice, F291 [02] AF40 1341 aix #{flash_page/2} ; since it's 128 bytes for GP32 F293 [03] 65E000 1342 cphx #boot_start ; check if finished F296 [03] 26D4 1343 bne MassErase1 ; loop back if not 1344 F298 [04] 81 1345 rts ; return 1346 1347 ;*************************************************** ***************** 1348 ; delay Subroutine 1349 ; 1350 ; This subroutine performs a simple software delay loop based upon 1351 ; the value passed in ACC. 1352 ; The following timing calculation applies: 1353 ; 1354 ; delay = ((ACC * 74) + 12) (tcyc) 1355 ; If A=1 1356 ; then delay = 11.7us at 114.545ns/cycle 1357 ; 1358 ;*************************************************** ***************** 1359 _delay: F299 [02] 87 1360 psha ; [2] save delay parameter temporarily 1361 delay1: F29A [02] A666 1362 lda #102T ; [2] initialize 5us loop counter 1363 ; (repeat for timing) 1364 delay2: F29C [03] 4BFE 1365 dbnza delay2 ; [3] decrement inner delay loop counter HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 34 F29E [06] 9E6B01F8 1366 dbnz 1,sp,delay1 ; [6] decrement outer delay loop counter F2A2 [02] 86 1367 pula ; [2] deallocate local variable F2A3 [04] 81 1368 rts ; [4] return 1369 F2A4 1370 EraseRamSize equ (*-MassErase) F2A4 1371 ProgramRam equ (*-_delay) 1372 1373 ;*************************************************** ***************** 1374 ; Flash Program Subroutine 1375 ; 1376 ; This subroutine controls the Flash programmi ng sequence. A stack 1377 ; frame data block is passed to it in the format shown below. 1378 ; This subroutine is copied into and executed from RAM. 1379 ; 1380 ; | | <-sp (when called) 1381 ; | ReturnAddr msb | 1382 ; | ReturnAddr lsb | <-sp (upon return) 1383 ; | SRecSize | 1384 ; | SRecAddr msb | 1385 ; | SRecAddr lsb | 1386 ; | SRecData 00 | 1387 ; | SRecData 01 | etc.. 1388 ;*************************************************** ***************** 1389 FlashProgram: F2A4 [02] 95 1390 tsx ; get the Stack Pointer F2A5 [04] 3551 1391 sthx _temp_sp ; save it temporarily 1392 1393 ; Get S-Record size and use the Stack Pointer as the data source pointer. F2A7 [02] A702 1394 ais #2 ; SP points to SRecSize F2A9 [02] 86 1395 pula ; get SRecSize F2AA [03] B750 1396 sta _count ; save it temporarily 1397 1398 ; Establish H:X as the destination pointer. F2AC [02] 8A 1399 pulh ; get destination address msb F2AD [02] 88 1400 pulx ; get destination address lsb 1401 1402 ; Set PGM, read the Flash Block Protect Register and write anywhere 1403 ; in desired Flash row. F2AE [02] A601 1404 lda #PGM ; set PGM control bit F2B0 [04] C7FE08 1405 sta flcr ; in Flash Control Register F2B3 [04] C6FF7E 1406 lda flbpr ; read from Flash HCmon_v1.asm Assembled with CASM08Z 4/13/2003 10:56:29 PM PAGE 35 Block Protect Register F2B6 [02] F7 1407 sta ,x ; write any data to first Flash address 1408 1409 ; Wait for >10us, then set HVEN. F2B7 [02] A620 1410 LDA #tnvs F2B9 [03] 4BFE 1411 DBNZA * F2BB [02] A609 1412 lda #(PGM|HVEN) ; set HVEN control bit F2BD [04] C7FE08 1413 sta flcr ; in Flash Control Register 1414 1415 ; Wa